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* Create the `esp32c6-hal` package * Teach `esp-hal-common` about the ESP32-C6 * Get a number of peripheral drivers building for the ESP32-C6 bckup initial clocks_ii * Create the `esp32c6-hal` package C6: update * Simplify and fix the linker script update * C6: add I2S * Create the `esp32c6-hal` package * Teach `esp-hal-common` about the ESP32-C6 * Get a number of peripheral drivers building for the ESP32-C6 bckup initial clocks_ii * Create the `esp32c6-hal` package * C6: update * Simplify and fix the linker script * update * C6: add I2S * update * C6 Interrupts * C6: Update build.rs, linker scripts and initial examples * C6: RMT * Fix interrupt handling * Fix `ClockControl::configure` * C6: revert to I2S0 instead of just I2S * C6: rebase and update * RTC not buildable * Implement RWDT and SWD disable * C6: working LEDC * C6: working RMT * C6: add aes * C6: add mcpwm * C6: add rtc_cntln - not finished * C6: update and formatting * C6: add pcnt * C6: add examples and format * Remove inline assembly, fix interrupts and linker scripts * Remove unused features, update cargo config for atomic emu, misc cleanup * Get ADC building and example "working" (as much as it ever does) * Remove a bunch of unused constants which were copied from ESP-IDF * The `mcpwm` example now works correctly * Get `TWAI` peripheral driver building for C6 * Clean up the `rtc_cntl` module and get all the other HALs building again * Add the C6 to our CI workflow * Fix various things that have been missed when rebasing Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`) * C6: Small updates in wdt (#1) * C6: Update WDT * C6: Update examples with WDT update * Update `esp-println` dependency to fix build errors * Fix formatting issues causing pre-commit hook to fail * Get some more examples working * Working `ram` example * Sync with changes in `main` after rebasing * Working `embassy_spi` example * Use a git dependency for the PAC until we publish a release * Fix I2S for ESP32-C6 * Fix esp32c6 direct boot (#4) * Add direct boot support for C6 * Fix direct boot for c6 - Actually copy into rtc ram - remove dummy section that is no longer needed (was just a waste of flash space) - Move RTC stuff before the no load sections * Update RWDT and refactor RTC (#3) * C6: Update RWDT and add example, refactor RTC and add not-really-good example * Update based on review comments, resolve bunch of warnings and run cargo fmt * Update C6 esp-pacs rev commit * Fix clocks_ll/esp32c6.rs * Fix riscv interrupts * Remove clock_monitor example for now * RAM example works in direct-boot mode * Add a TODO for &mut TIMG0 and cargo fmt * Fix linker script after a bad rebase * Update CI and Cargo.toml embassy required features * use riscv32imac-unknown-none-elf target for C6 in CI * change default target to riscv32imac-unknown-none-elf * add riscv32imac-unknown-none-elf target to MSRV job * another cleanup --------- Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Jesse Braham <jesse@beta7.io> * Make required changes to include new `RADIO` peripheral * Use published versions of PAC and `esp-println` * Use the correct target extensions (`imac`) * Fix the super watchdog timer, plus a few more examples * Fix UART clock configuration * Make sure to sync UART registers when configuring AT cmd detection * Disable APM in direct-boot mode * Address a number of review comments * Fix `SPI` clocks and `rtc_watchdog` example (#6) * fix SPI clocks * run cargo fmt * Add comment about used default clk src * Fix rtc_watchdog example in BL mode * run cargo fmt * Update rtc_watchdog example that it works in DB mode * README and example fixes/cleanup * Add I2C peripheral enable and reset * Fix `ApbSarAdc` configuration in `system.rs` --------- Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com> Co-authored-by: Juraj Sadel <jurajsadel@gmail.com> Co-authored-by: Scott Mabin <scott@mabez.dev>
150 lines
4.4 KiB
Rust
150 lines
4.4 KiB
Rust
//! PCNT Encoder Demo
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//!
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//! This example decodes a quadrature encoder
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//!
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//! Since the PCNT units reset to zero when they reach their limits
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//! we enable an interrupt on the upper and lower limits and
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//! track the overflow in an AtomicI32
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#![no_std]
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#![no_main]
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use core::{
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cell::RefCell,
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cmp::min,
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sync::atomic::{AtomicI32, Ordering},
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};
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use critical_section::Mutex;
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use esp32c6_hal as esp_hal;
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use esp_backtrace as _;
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use esp_hal::{
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clock::ClockControl,
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interrupt,
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pcnt::{channel, channel::PcntSource, unit, PCNT},
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peripherals::{self, Peripherals},
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prelude::*,
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timer::TimerGroup,
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Rtc,
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IO,
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};
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use esp_println::println;
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static UNIT0: Mutex<RefCell<Option<unit::Unit>>> = Mutex::new(RefCell::new(None));
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static VALUE: AtomicI32 = AtomicI32::new(0);
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take();
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let mut system = peripherals.PCR.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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// Disable the watchdog timers. For the ESP32-C6, this includes the Super WDT,
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// and the TIMG WDTs.
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let mut rtc = Rtc::new(peripherals.LP_CLKRST);
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt0 = timer_group0.wdt;
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let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
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let mut wdt1 = timer_group1.wdt;
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// Disable watchdog timers
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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wdt1.disable();
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let unit_number = unit::Number::Unit1;
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// setup a pulse couter
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println!("setup pulse counter unit 0");
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let pcnt = PCNT::new(peripherals.PCNT, &mut system.peripheral_clock_control);
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let mut u0 = pcnt.get_unit(unit_number);
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u0.configure(unit::Config {
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low_limit: -100,
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high_limit: 100,
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filter: Some(min(10u16 * 80, 1023u16)),
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..Default::default()
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})
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.unwrap();
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println!("setup channel 0");
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let mut ch0 = u0.get_channel(channel::Number::Channel0);
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let mut pin_a = io.pins.gpio5.into_pull_up_input();
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let mut pin_b = io.pins.gpio6.into_pull_up_input();
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ch0.configure(
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PcntSource::from_pin(&mut pin_a),
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PcntSource::from_pin(&mut pin_b),
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channel::Config {
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lctrl_mode: channel::CtrlMode::Reverse,
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hctrl_mode: channel::CtrlMode::Keep,
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pos_edge: channel::EdgeMode::Decrement,
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neg_edge: channel::EdgeMode::Increment,
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invert_ctrl: false,
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invert_sig: false,
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},
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);
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println!("setup channel 1");
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let mut ch1 = u0.get_channel(channel::Number::Channel1);
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ch1.configure(
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PcntSource::from_pin(&mut pin_b),
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PcntSource::from_pin(&mut pin_a),
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channel::Config {
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lctrl_mode: channel::CtrlMode::Reverse,
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hctrl_mode: channel::CtrlMode::Keep,
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pos_edge: channel::EdgeMode::Increment,
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neg_edge: channel::EdgeMode::Decrement,
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invert_ctrl: false,
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invert_sig: false,
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},
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);
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println!("subscribing to events");
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u0.events(unit::Events {
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low_limit: true,
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high_limit: true,
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thresh0: false,
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thresh1: false,
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zero: false,
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});
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println!("enabling interrupts");
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u0.listen();
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println!("resume pulse counter unit 0");
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u0.resume();
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critical_section::with(|cs| UNIT0.borrow_ref_mut(cs).replace(u0));
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interrupt::enable(peripherals::Interrupt::PCNT, interrupt::Priority::Priority2).unwrap();
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let mut last_value: i32 = 0;
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loop {
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critical_section::with(|cs| {
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let mut u0 = UNIT0.borrow_ref_mut(cs);
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let u0 = u0.as_mut().unwrap();
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let value: i32 = u0.get_value() as i32 + VALUE.load(Ordering::SeqCst);
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if value != last_value {
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println!("value: {value}");
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last_value = value;
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}
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});
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}
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}
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#[interrupt]
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fn PCNT() {
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critical_section::with(|cs| {
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let mut u0 = UNIT0.borrow_ref_mut(cs);
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let u0 = u0.as_mut().unwrap();
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if u0.interrupt_set() {
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let events = u0.get_events();
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if events.high_limit {
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VALUE.fetch_add(100, Ordering::SeqCst);
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} else if events.low_limit {
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VALUE.fetch_add(-100, Ordering::SeqCst);
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}
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u0.reset_interrupt();
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}
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});
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}
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