esp-hal/esp32c6-hal/examples/pcnt_encoder.rs
Jesse Braham d293d9f162
Add support for the ESP32-C6 (#392)
* Create the `esp32c6-hal` package

* Teach `esp-hal-common` about the ESP32-C6

* Get a number of peripheral drivers building for the ESP32-C6

bckup

initial clocks_ii

* Create the `esp32c6-hal` package

C6: update

* Simplify and fix the linker script

update

* C6: add I2S

* Create the `esp32c6-hal` package

* Teach `esp-hal-common` about the ESP32-C6

* Get a number of peripheral drivers building for the ESP32-C6

bckup

initial clocks_ii

* Create the `esp32c6-hal` package

* C6: update

* Simplify and fix the linker script

* update

* C6: add I2S

* update

* C6 Interrupts

* C6: Update build.rs, linker scripts and initial examples

* C6: RMT

* Fix interrupt handling

* Fix `ClockControl::configure`

* C6: revert to I2S0 instead of just I2S

* C6: rebase and update

* RTC not buildable

* Implement RWDT and SWD disable

* C6: working LEDC

* C6: working RMT

* C6: add aes

* C6: add mcpwm

* C6: add rtc_cntln - not finished

* C6: update and formatting

* C6: add pcnt

* C6: add examples and format

* Remove inline assembly, fix interrupts and linker scripts

* Remove unused features, update cargo config for atomic emu, misc cleanup

* Get ADC building and example "working" (as much as it ever does)

* Remove a bunch of unused constants which were copied from ESP-IDF

* The `mcpwm` example now works correctly

* Get `TWAI` peripheral driver building for C6

* Clean up the `rtc_cntl` module and get all the other HALs building again

* Add the C6 to our CI workflow

* Fix various things that have been missed when rebasing

Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`)

* C6: Small updates in wdt (#1)

* C6: Update WDT

* C6: Update examples with WDT update

* Update `esp-println` dependency to fix build errors

* Fix formatting issues causing pre-commit hook to fail

* Get some more examples working

* Working `ram` example

* Sync with changes in `main` after rebasing

* Working `embassy_spi` example

* Use a git dependency for the PAC until we publish a release

* Fix I2S for ESP32-C6

* Fix esp32c6 direct boot (#4)

* Add direct boot support for C6

* Fix direct boot for c6

- Actually copy into rtc ram
- remove dummy section that is no longer needed (was just a waste of
  flash space)
- Move RTC stuff before the no load sections

* Update RWDT and refactor RTC (#3)

* C6: Update RWDT and add example, refactor RTC and add not-really-good example

* Update based on review comments, resolve bunch of warnings and run cargo fmt

* Update C6 esp-pacs rev commit

* Fix clocks_ll/esp32c6.rs

* Fix riscv interrupts

* Remove clock_monitor example for now

* RAM example works in direct-boot mode

* Add a TODO for &mut TIMG0 and cargo fmt

* Fix linker script after a bad rebase

* Update CI and Cargo.toml embassy required features

* use riscv32imac-unknown-none-elf target for C6 in CI

* change default target to riscv32imac-unknown-none-elf

* add riscv32imac-unknown-none-elf target to MSRV job

* another cleanup

---------

Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Jesse Braham <jesse@beta7.io>

* Make required changes to include new `RADIO` peripheral

* Use published versions of PAC and `esp-println`

* Use the correct target extensions (`imac`)

* Fix the super watchdog timer, plus a few more examples

* Fix UART clock configuration

* Make sure to sync UART registers when configuring AT cmd detection

* Disable APM in direct-boot mode

* Address a number of review comments

* Fix `SPI` clocks and `rtc_watchdog` example  (#6)

* fix SPI clocks

* run cargo fmt

* Add comment about used default clk src

* Fix rtc_watchdog example in BL mode

* run cargo fmt

* Update rtc_watchdog example that it works in DB mode

* README and example fixes/cleanup

* Add I2C peripheral enable and reset

* Fix `ApbSarAdc` configuration in `system.rs`

---------

Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
2023-02-27 09:15:44 -08:00

150 lines
4.4 KiB
Rust

//! PCNT Encoder Demo
//!
//! This example decodes a quadrature encoder
//!
//! Since the PCNT units reset to zero when they reach their limits
//! we enable an interrupt on the upper and lower limits and
//! track the overflow in an AtomicI32
#![no_std]
#![no_main]
use core::{
cell::RefCell,
cmp::min,
sync::atomic::{AtomicI32, Ordering},
};
use critical_section::Mutex;
use esp32c6_hal as esp_hal;
use esp_backtrace as _;
use esp_hal::{
clock::ClockControl,
interrupt,
pcnt::{channel, channel::PcntSource, unit, PCNT},
peripherals::{self, Peripherals},
prelude::*,
timer::TimerGroup,
Rtc,
IO,
};
use esp_println::println;
static UNIT0: Mutex<RefCell<Option<unit::Unit>>> = Mutex::new(RefCell::new(None));
static VALUE: AtomicI32 = AtomicI32::new(0);
#[entry]
fn main() -> ! {
let peripherals = Peripherals::take();
let mut system = peripherals.PCR.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C6, this includes the Super WDT,
// and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.LP_CLKRST);
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
let mut wdt0 = timer_group0.wdt;
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
let mut wdt1 = timer_group1.wdt;
// Disable watchdog timers
rtc.swd.disable();
rtc.rwdt.disable();
wdt0.disable();
wdt1.disable();
let unit_number = unit::Number::Unit1;
// setup a pulse couter
println!("setup pulse counter unit 0");
let pcnt = PCNT::new(peripherals.PCNT, &mut system.peripheral_clock_control);
let mut u0 = pcnt.get_unit(unit_number);
u0.configure(unit::Config {
low_limit: -100,
high_limit: 100,
filter: Some(min(10u16 * 80, 1023u16)),
..Default::default()
})
.unwrap();
println!("setup channel 0");
let mut ch0 = u0.get_channel(channel::Number::Channel0);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut pin_a = io.pins.gpio5.into_pull_up_input();
let mut pin_b = io.pins.gpio6.into_pull_up_input();
ch0.configure(
PcntSource::from_pin(&mut pin_a),
PcntSource::from_pin(&mut pin_b),
channel::Config {
lctrl_mode: channel::CtrlMode::Reverse,
hctrl_mode: channel::CtrlMode::Keep,
pos_edge: channel::EdgeMode::Decrement,
neg_edge: channel::EdgeMode::Increment,
invert_ctrl: false,
invert_sig: false,
},
);
println!("setup channel 1");
let mut ch1 = u0.get_channel(channel::Number::Channel1);
ch1.configure(
PcntSource::from_pin(&mut pin_b),
PcntSource::from_pin(&mut pin_a),
channel::Config {
lctrl_mode: channel::CtrlMode::Reverse,
hctrl_mode: channel::CtrlMode::Keep,
pos_edge: channel::EdgeMode::Increment,
neg_edge: channel::EdgeMode::Decrement,
invert_ctrl: false,
invert_sig: false,
},
);
println!("subscribing to events");
u0.events(unit::Events {
low_limit: true,
high_limit: true,
thresh0: false,
thresh1: false,
zero: false,
});
println!("enabling interrupts");
u0.listen();
println!("resume pulse counter unit 0");
u0.resume();
critical_section::with(|cs| UNIT0.borrow_ref_mut(cs).replace(u0));
interrupt::enable(peripherals::Interrupt::PCNT, interrupt::Priority::Priority2).unwrap();
let mut last_value: i32 = 0;
loop {
critical_section::with(|cs| {
let mut u0 = UNIT0.borrow_ref_mut(cs);
let u0 = u0.as_mut().unwrap();
let value: i32 = u0.get_value() as i32 + VALUE.load(Ordering::SeqCst);
if value != last_value {
println!("value: {value}");
last_value = value;
}
});
}
}
#[interrupt]
fn PCNT() {
critical_section::with(|cs| {
let mut u0 = UNIT0.borrow_ref_mut(cs);
let u0 = u0.as_mut().unwrap();
if u0.interrupt_set() {
let events = u0.get_events();
if events.high_limit {
VALUE.fetch_add(100, Ordering::SeqCst);
} else if events.low_limit {
VALUE.fetch_add(-100, Ordering::SeqCst);
}
u0.reset_interrupt();
}
});
}