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* Create the `esp32c6-hal` package * Teach `esp-hal-common` about the ESP32-C6 * Get a number of peripheral drivers building for the ESP32-C6 bckup initial clocks_ii * Create the `esp32c6-hal` package C6: update * Simplify and fix the linker script update * C6: add I2S * Create the `esp32c6-hal` package * Teach `esp-hal-common` about the ESP32-C6 * Get a number of peripheral drivers building for the ESP32-C6 bckup initial clocks_ii * Create the `esp32c6-hal` package * C6: update * Simplify and fix the linker script * update * C6: add I2S * update * C6 Interrupts * C6: Update build.rs, linker scripts and initial examples * C6: RMT * Fix interrupt handling * Fix `ClockControl::configure` * C6: revert to I2S0 instead of just I2S * C6: rebase and update * RTC not buildable * Implement RWDT and SWD disable * C6: working LEDC * C6: working RMT * C6: add aes * C6: add mcpwm * C6: add rtc_cntln - not finished * C6: update and formatting * C6: add pcnt * C6: add examples and format * Remove inline assembly, fix interrupts and linker scripts * Remove unused features, update cargo config for atomic emu, misc cleanup * Get ADC building and example "working" (as much as it ever does) * Remove a bunch of unused constants which were copied from ESP-IDF * The `mcpwm` example now works correctly * Get `TWAI` peripheral driver building for C6 * Clean up the `rtc_cntl` module and get all the other HALs building again * Add the C6 to our CI workflow * Fix various things that have been missed when rebasing Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`) * C6: Small updates in wdt (#1) * C6: Update WDT * C6: Update examples with WDT update * Update `esp-println` dependency to fix build errors * Fix formatting issues causing pre-commit hook to fail * Get some more examples working * Working `ram` example * Sync with changes in `main` after rebasing * Working `embassy_spi` example * Use a git dependency for the PAC until we publish a release * Fix I2S for ESP32-C6 * Fix esp32c6 direct boot (#4) * Add direct boot support for C6 * Fix direct boot for c6 - Actually copy into rtc ram - remove dummy section that is no longer needed (was just a waste of flash space) - Move RTC stuff before the no load sections * Update RWDT and refactor RTC (#3) * C6: Update RWDT and add example, refactor RTC and add not-really-good example * Update based on review comments, resolve bunch of warnings and run cargo fmt * Update C6 esp-pacs rev commit * Fix clocks_ll/esp32c6.rs * Fix riscv interrupts * Remove clock_monitor example for now * RAM example works in direct-boot mode * Add a TODO for &mut TIMG0 and cargo fmt * Fix linker script after a bad rebase * Update CI and Cargo.toml embassy required features * use riscv32imac-unknown-none-elf target for C6 in CI * change default target to riscv32imac-unknown-none-elf * add riscv32imac-unknown-none-elf target to MSRV job * another cleanup --------- Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Jesse Braham <jesse@beta7.io> * Make required changes to include new `RADIO` peripheral * Use published versions of PAC and `esp-println` * Use the correct target extensions (`imac`) * Fix the super watchdog timer, plus a few more examples * Fix UART clock configuration * Make sure to sync UART registers when configuring AT cmd detection * Disable APM in direct-boot mode * Address a number of review comments * Fix `SPI` clocks and `rtc_watchdog` example (#6) * fix SPI clocks * run cargo fmt * Add comment about used default clk src * Fix rtc_watchdog example in BL mode * run cargo fmt * Update rtc_watchdog example that it works in DB mode * README and example fixes/cleanup * Add I2C peripheral enable and reset * Fix `ApbSarAdc` configuration in `system.rs` --------- Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com> Co-authored-by: Juraj Sadel <jurajsadel@gmail.com> Co-authored-by: Scott Mabin <scott@mabez.dev>
113 lines
2.2 KiB
Rust
113 lines
2.2 KiB
Rust
#![no_std]
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pub use embedded_hal as ehal;
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#[cfg(feature = "embassy")]
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pub use esp_hal_common::embassy;
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pub use esp_hal_common::{
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aes,
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analog::adc::implementation as adc,
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clock,
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dma,
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dma::gdma,
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efuse,
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entry,
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gpio,
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i2c,
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i2s,
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interrupt,
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ledc,
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macros,
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mcpwm,
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pcnt,
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peripherals,
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prelude,
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pulse_control,
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riscv,
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sha,
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spi,
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systimer,
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timer,
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trapframe,
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twai,
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uart,
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utils,
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Cpu,
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Delay,
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PulseControl,
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Rtc,
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Rwdt,
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Uart,
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UsbSerialJtag,
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};
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pub use self::gpio::IO;
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/// Common module for analog functions
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pub mod analog {
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pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt};
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}
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extern "C" {
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// Boundaries of the .iram section
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static mut _srwtext: u32;
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static mut _erwtext: u32;
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static mut _irwtext: u32;
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// Boundaries of the .bss section
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static mut _ebss: u32;
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static mut _sbss: u32;
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// Boundaries of the rtc .bss section
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static mut _rtc_fast_bss_start: u32;
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static mut _rtc_fast_bss_end: u32;
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// Boundaries of the .rtc_fast.text section
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static mut _srtc_fast_text: u32;
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static mut _ertc_fast_text: u32;
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static mut _irtc_fast_text: u32;
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// Boundaries of the .rtc_fast.data section
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static mut _rtc_fast_data_start: u32;
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static mut _rtc_fast_data_end: u32;
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static mut _irtc_fast_data: u32;
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}
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#[cfg(feature = "direct-boot")]
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#[doc(hidden)]
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#[esp_hal_common::esp_riscv_rt::pre_init]
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unsafe fn init() {
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r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext);
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r0::init_data(
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&mut _rtc_fast_data_start,
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&mut _rtc_fast_data_end,
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&_irtc_fast_data,
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);
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r0::init_data(&mut _srtc_fast_text, &mut _ertc_fast_text, &_irtc_fast_text);
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esp_hal_common::disable_apm_filter();
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}
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#[allow(unreachable_code)]
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#[export_name = "_mp_hook"]
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#[doc(hidden)]
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pub fn mp_hook() -> bool {
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unsafe {
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r0::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
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}
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#[cfg(feature = "direct-boot")]
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return true;
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// no init data when using normal boot - but we need to zero out BSS
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unsafe {
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r0::zero_bss(&mut _sbss, &mut _ebss);
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}
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false
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}
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#[no_mangle]
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extern "C" fn EspDefaultHandler(_interrupt: peripherals::Interrupt) {}
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