mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 06:40:47 +00:00
1789780d06
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
106 lines
2.9 KiB
Rust
106 lines
2.9 KiB
Rust
//! This shows how to use RTC memory.
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//! RTC memory is retained during resets and during most sleep modes.
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//! Initialized memory is always re-initialized on startup.
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//! Uninitialzed memory isn't initialized on startup and can be used to keep
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//! data during resets. Zeroed memory is initialized to zero on startup.
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//! We can also run code from RTC memory.
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#![no_std]
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#![no_main]
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use core::fmt::Write;
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use esp32_hal::{
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clock::ClockControl,
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macros::ram,
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pac::{Peripherals, UART0},
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prelude::*,
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timer::TimerGroup,
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Serial,
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};
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use nb::block;
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use panic_halt as _;
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use xtensa_lx_rt::entry;
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#[ram(rtc_fast)]
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static mut SOME_INITED_DATA: [u8; 2] = [0xaa, 0xbb];
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#[ram(rtc_fast, uninitialized)]
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static mut SOME_UNINITED_DATA: [u8; 2] = [0; 2];
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#[ram(rtc_fast, zeroed)]
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static mut SOME_ZEROED_DATA: [u8; 8] = [0; 8];
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let system = peripherals.DPORT.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut timer0 = timer_group0.timer0;
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let mut wdt = timer_group0.wdt;
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let mut serial0 = Serial::new(peripherals.UART0);
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// Disable MWDT flash boot protection
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wdt.disable();
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// The RWDT flash boot protection remains enabled and it being triggered is part
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// of the example
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timer0.start(1u64.secs());
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writeln!(
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serial0,
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"IRAM function located at {:p}",
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function_in_ram as *const ()
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)
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.unwrap();
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unsafe {
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writeln!(serial0, "SOME_INITED_DATA {:x?}", SOME_INITED_DATA).unwrap();
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writeln!(serial0, "SOME_UNINITED_DATA {:x?}", SOME_UNINITED_DATA).unwrap();
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writeln!(serial0, "SOME_ZEROED_DATA {:x?}", SOME_ZEROED_DATA).unwrap();
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SOME_INITED_DATA[0] = 0xff;
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SOME_ZEROED_DATA[0] = 0xff;
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writeln!(serial0, "SOME_INITED_DATA {:x?}", SOME_INITED_DATA).unwrap();
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writeln!(serial0, "SOME_UNINITED_DATA {:x?}", SOME_UNINITED_DATA).unwrap();
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writeln!(serial0, "SOME_ZEROED_DATA {:x?}", SOME_ZEROED_DATA).unwrap();
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if SOME_UNINITED_DATA[0] != 0 {
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SOME_UNINITED_DATA[0] = 0;
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SOME_UNINITED_DATA[1] = 0;
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}
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if SOME_UNINITED_DATA[1] == 0xff {
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SOME_UNINITED_DATA[1] = 0;
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}
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writeln!(serial0, "Counter {}", SOME_UNINITED_DATA[1]).unwrap();
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SOME_UNINITED_DATA[1] += 1;
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}
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writeln!(
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serial0,
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"RTC_FAST function located at {:p}",
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function_in_rtc_ram as *const ()
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)
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.unwrap();
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writeln!(serial0, "Result {}", function_in_rtc_ram()).unwrap();
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loop {
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function_in_ram(&mut serial0);
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block!(timer0.wait()).unwrap();
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}
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}
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#[ram]
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fn function_in_ram(serial0: &mut Serial<UART0>) {
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writeln!(serial0, "Hello world!").unwrap();
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}
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#[ram(rtc_fast)]
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fn function_in_rtc_ram() -> u32 {
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42
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}
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