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https://github.com/esp-rs/esp-hal.git
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e97de69b42
* use 1.87 in CI, bump MSRV to 1.86 * update API baseline files (rustdoc json format change) * Add api-baseline regen guide to guidelines
30 lines
884 B
TOML
30 lines
884 B
TOML
[package]
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name = "esp-riscv-rt"
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version = "0.10.0"
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edition = "2024"
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rust-version = "1.86.0"
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description = "Minimal runtime / startup for RISC-V CPUs from Espressif"
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documentation = "https://docs.espressif.com/projects/rust/esp-riscv-rt/latest/"
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keywords = ["esp32", "espressif", "riscv", "runtime", "startup"]
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categories = ["embedded", "hardware-support", "no-std"]
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repository = "https://github.com/esp-rs/esp-hal"
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license = "MIT OR Apache-2.0"
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[lib]
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bench = false
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test = false
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[dependencies]
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document-features = "0.2.11"
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riscv = "0.12.1"
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riscv-rt-macros = "0.4.0"
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[features]
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## Indicate that the device supports `mie` and `mip` instructions.
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has-mie-mip = []
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## Indicate that the device has RTC RAM.
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rtc-ram = []
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# This feature is intended for testing; you probably don't want to enable it:
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ci = ["has-mie-mip", "rtc-ram"]
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