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171e66e87a
* feat: relocate riscv isr to iram Previously, the trap vector itself and its immediate callees (`_start_trap` and `_start_trap_rust_hal`) were located in the mapped instruction flash range `0x420..`, increasing cache pressure and adding variable latency to the very beginning of the interrupt/exception service flow. This change places those routines in iram directly: ``` Num: Value Size Type Bind Vis Ndx Name 48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal 48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust 48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table 48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap 48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap ``` As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx` * feat(riscv): place .trap in RAM This change follows through on relocating the `_vector_table`, `_start_trap`, and `_start_trap_rust` functions for all present build/link modes for the 'c2, 'c3, 'c6, and 'h2. It has been tested by running the `software_interrupts` example for the 'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to identify how to run the `mcu-boot` mode for the 'c3, nor do I have present access to any of the other devices for testing. * docs: Update CHANGELOG.md