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69776eb638
* Abstract out LP-core targeting packages * Encode targets_lp_core in Cargo.toml * Encode architecture compatibility in Cargo.toml * Move semver_checked into Cargo.toml * Cache parsed tomls * Parse simple feature sets from Cargo.toml * Move all basic feature rules to Cargo.toml * Add check configs * Limit command length on Windows * Update cargo.rs * Add clippy configs * Use a single syntax, use a single doc-config line * Fix known problems * Run cargo check in CI command * Fix more problems * Fix esp-storage
24 lines
688 B
TOML
24 lines
688 B
TOML
[package]
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name = "xtensa-lx"
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version = "0.12.0"
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edition = "2024"
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rust-version = "1.86.0"
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description = "Low-level access to Xtensa LX processors and peripherals"
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documentation = "https://docs.espressif.com/projects/rust/xtensa-lx/latest/"
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repository = "https://github.com/esp-rs/esp-hal"
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license = "MIT OR Apache-2.0"
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categories = ["embedded", "hardware-support", "no-std"]
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keywords = ["lx", "peripheral", "register", "xtensa"]
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[package.metadata.espressif]
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requires_target = ["xtensa-esp32-none-elf", "xtensa-esp32s2-none-elf", "xtensa-esp32s3-none-elf"]
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[lib]
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bench = false
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test = false
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[dependencies]
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critical-section = "1.2.0"
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[features]
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