mirror of
https://github.com/esp-rs/esp-idf-hal.git
synced 2025-09-30 05:41:12 +00:00
Disable interrupts in the ISR callback; #296
This commit is contained in:
ivmarkov
parent
4381d62aed
commit
1a0f3a1dad
203
src/gpio.rs
203
src/gpio.rs
@ -1145,30 +1145,11 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
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{
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extern crate alloc;
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self.unsubscribe()?;
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self.disable_interrupt()?;
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let callback: alloc::boxed::Box<dyn FnMut() + 'static> = alloc::boxed::Box::new(callback);
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chip::PIN_ISR_HANDLER[self.pin.pin() as usize] = Some(alloc::boxed::Box::new(callback));
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self.internal_subscribe()
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}
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#[cfg(not(feature = "riscv-ulp-hal"))]
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fn internal_subscribe(&mut self) -> Result<(), EspError>
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where
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MODE: InputMode,
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{
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enable_isr_service()?;
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unsafe {
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esp!(gpio_isr_handler_add(
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self.pin.pin(),
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Some(Self::handle_isr),
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self.pin.pin() as u32 as *mut core::ffi::c_void,
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))?;
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}
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Ok(())
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self.enable_interrupt()
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}
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#[cfg(not(feature = "riscv-ulp-hal"))]
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@ -1183,14 +1164,28 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
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Ok(())
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}
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/// Enables or re-enables the interrupt
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///
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/// Note that the interrupt is automatically disabled each time an interrupt is triggered
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/// (or else we risk entering a constant interrupt processing loop while the pin is in low/high state
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/// and the interrupt type is set to non-edge)
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///
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/// Therefore - to continue receiving ISR interrupts - user needs to call `enable_interrupt`
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/// - **from a non-ISR context** - after each successful interrupt triggering.
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub fn enable_interrupt(&mut self) -> Result<(), EspError>
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where
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MODE: InputMode,
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{
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esp!(unsafe { gpio_intr_enable(self.pin.pin()) })?;
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enable_isr_service()?;
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Ok(())
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unsafe {
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esp!(gpio_isr_handler_add(
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self.pin.pin(),
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Some(Self::handle_isr),
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self.pin.pin() as u32 as *mut core::ffi::c_void,
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))
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}
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}
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#[cfg(not(feature = "riscv-ulp-hal"))]
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@ -1198,7 +1193,11 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
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where
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MODE: InputMode,
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{
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esp!(unsafe { gpio_intr_disable(self.pin.pin()) })?;
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use core::sync::atomic::Ordering;
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if ISR_SERVICE_ENABLED.load(Ordering::SeqCst) {
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esp!(unsafe { gpio_isr_handler_remove(self.pin.pin()) })?;
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}
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Ok(())
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}
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@ -1208,10 +1207,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
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where
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MODE: InputMode,
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{
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use core::sync::atomic::Ordering;
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esp!(unsafe { gpio_set_intr_type(self.pin.pin(), interrupt_type.into()) })?;
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PIN_INTER[self.pin.pin() as usize].store(interrupt_type.into(), Ordering::SeqCst);
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Ok(())
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}
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@ -1220,6 +1216,11 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
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unsafe extern "C" fn handle_isr(user_ctx: *mut core::ffi::c_void) {
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let pin = user_ctx as u32;
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// IMPORTANT: MUST be done or else the ESP IDF GPIO driver will continue calling us in a loop
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// - particularly when the interrupt type is set to non-edge triggering (pin high or low) -
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// which will eventually cause the Interrupt WatchDog to kick in
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gpio_intr_disable(pin as _);
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PIN_NOTIF[pin as usize].notify_lsb();
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#[cfg(feature = "alloc")]
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@ -1233,81 +1234,53 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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impl<T: Pin, MODE: InputMode> PinDriver<'_, T, MODE> {
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pub async fn wait_for(
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&mut self,
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interrupt_type: InterruptType,
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honor_already_triggered: bool,
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) -> Result<(), EspError> {
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use core::sync::atomic::Ordering;
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if chip::PIN_INTER[self.pin.pin() as usize].load(Ordering::SeqCst) != interrupt_type.into()
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{
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self.unsubscribe()?;
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self.internal_subscribe()?;
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self.set_interrupt_type(interrupt_type)?;
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self.enable_interrupt()?;
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}
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pub async fn wait_for(&mut self, interrupt_type: InterruptType) -> Result<(), EspError> {
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self.disable_interrupt()?;
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let notif = &chip::PIN_NOTIF[self.pin.pin() as usize];
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if !honor_already_triggered {
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notif.reset();
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}
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notif.reset();
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match interrupt_type {
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InterruptType::LowLevel => {
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if self.is_low() {
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notif.reset();
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return Ok(());
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}
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}
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InterruptType::HighLevel => {
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if self.is_high() {
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notif.reset();
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return Ok(());
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}
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}
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_ => (),
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}
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self.set_interrupt_type(interrupt_type)?;
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self.enable_interrupt()?;
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notif.wait().await;
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Ok(())
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}
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pub async fn wait_for_high(&mut self, honor_already_triggered: bool) -> Result<(), EspError> {
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self.wait_for(InterruptType::HighLevel, honor_already_triggered)
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.await
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pub async fn wait_for_high(&mut self) -> Result<(), EspError> {
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self.wait_for(InterruptType::HighLevel).await
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}
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pub async fn wait_for_low(&mut self, honor_already_triggered: bool) -> Result<(), EspError> {
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self.wait_for(InterruptType::LowLevel, honor_already_triggered)
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.await
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pub async fn wait_for_low(&mut self) -> Result<(), EspError> {
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self.wait_for(InterruptType::LowLevel).await
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}
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pub async fn wait_for_rising_edge(
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&mut self,
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honor_already_triggered: bool,
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) -> Result<(), EspError> {
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self.wait_for(InterruptType::PosEdge, honor_already_triggered)
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.await
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pub async fn wait_for_rising_edge(&mut self) -> Result<(), EspError> {
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self.wait_for(InterruptType::PosEdge).await
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}
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pub async fn wait_for_falling_edge(
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&mut self,
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honor_already_triggered: bool,
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) -> Result<(), EspError> {
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self.wait_for(InterruptType::NegEdge, honor_already_triggered)
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.await
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pub async fn wait_for_falling_edge(&mut self) -> Result<(), EspError> {
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self.wait_for(InterruptType::NegEdge).await
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}
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pub async fn wait_for_any_edge(
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&mut self,
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honor_already_triggered: bool,
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) -> Result<(), EspError> {
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self.wait_for(InterruptType::AnyEdge, honor_already_triggered)
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.await
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pub async fn wait_for_any_edge(&mut self) -> Result<(), EspError> {
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self.wait_for(InterruptType::AnyEdge).await
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}
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}
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@ -1440,31 +1413,31 @@ where
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "nightly"))]
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impl<T: Pin, MODE: InputMode> embedded_hal_async::digital::Wait for PinDriver<'_, T, MODE> {
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async fn wait_for_high(&mut self) -> Result<(), GpioError> {
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self.wait_for_high(false).await?;
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self.wait_for_high().await?;
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Ok(())
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}
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async fn wait_for_low(&mut self) -> Result<(), GpioError> {
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self.wait_for_low(false).await?;
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self.wait_for_low().await?;
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Ok(())
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}
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async fn wait_for_rising_edge(&mut self) -> Result<(), GpioError> {
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self.wait_for_rising_edge(false).await?;
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self.wait_for_rising_edge().await?;
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Ok(())
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}
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async fn wait_for_falling_edge(&mut self) -> Result<(), GpioError> {
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self.wait_for_falling_edge(false).await?;
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self.wait_for_falling_edge().await?;
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Ok(())
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}
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async fn wait_for_any_edge(&mut self) -> Result<(), GpioError> {
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self.wait_for_any_edge(false).await?;
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self.wait_for_any_edge().await?;
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Ok(())
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}
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@ -1536,18 +1509,15 @@ unsafe fn reset_pin(_pin: i32, _mode: gpio_mode_t) -> Result<(), EspError> {
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unsafe fn unsubscribe_pin(pin: i32) -> Result<(), EspError> {
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use core::sync::atomic::Ordering;
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enable_isr_service()?;
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if ISR_SERVICE_ENABLED.load(Ordering::SeqCst) {
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esp!(gpio_isr_handler_remove(pin))?;
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esp!(gpio_intr_disable(pin))?;
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esp!(gpio_set_intr_type(pin, gpio_int_type_t_GPIO_INTR_DISABLE))?;
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esp!(gpio_isr_handler_remove(pin))?;
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chip::PIN_NOTIF[pin as usize].reset();
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chip::PIN_INTER[pin as usize].store(gpio_int_type_t_GPIO_INTR_DISABLE as u8, Ordering::SeqCst);
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chip::PIN_NOTIF[pin as usize].reset();
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#[cfg(feature = "alloc")]
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{
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chip::PIN_ISR_HANDLER[pin as usize] = None;
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#[cfg(feature = "alloc")]
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{
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chip::PIN_ISR_HANDLER[pin as usize] = None;
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}
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}
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Ok(())
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@ -1555,12 +1525,7 @@ unsafe fn unsubscribe_pin(pin: i32) -> Result<(), EspError> {
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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#[allow(clippy::declare_interior_mutable_const)] // OK because this is only used as an array initializer
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const PIN_ISR_INIT: Option<alloc::boxed::Box<alloc::boxed::Box<dyn FnMut()>>> = None;
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#[cfg(not(feature = "riscv-ulp-hal"))]
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#[allow(clippy::declare_interior_mutable_const)] // OK because this is only used as an array initializer
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const PIN_INTER_INIT: core::sync::atomic::AtomicU8 =
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core::sync::atomic::AtomicU8::new(gpio_int_type_t_GPIO_INTR_DISABLE as u8);
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const PIN_ISR_INIT: Option<alloc::boxed::Box<dyn FnMut()>> = None;
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#[cfg(not(feature = "riscv-ulp-hal"))]
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#[allow(clippy::declare_interior_mutable_const)] // OK because this is only used as an array initializer
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@ -1700,9 +1665,6 @@ macro_rules! pin {
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#[cfg(esp32)]
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mod chip {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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use core::sync::atomic::AtomicU8;
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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extern crate alloc;
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@ -1724,11 +1686,7 @@ mod chip {
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#[allow(clippy::type_complexity)]
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<Box<dyn FnMut()>>>; 40] = [PIN_ISR_INIT; 40];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_INTER: [AtomicU8; 40] = [PIN_INTER_INIT; 40];
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<dyn FnMut()>>; 40] = [PIN_ISR_INIT; 40];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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@ -1904,9 +1862,6 @@ mod chip {
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#[cfg(any(esp32s2, esp32s3))] // TODO: Implement proper pin layout for esp32c6 and esp32p4
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mod chip {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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use core::sync::atomic::AtomicU8;
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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extern crate alloc;
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@ -1928,11 +1883,7 @@ mod chip {
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#[allow(clippy::type_complexity)]
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<Box<dyn FnMut()>>>; 49] = [PIN_ISR_INIT; 49];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_INTER: [AtomicU8; 49] = [PIN_INTER_INIT; 49];
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<dyn FnMut()>>; 49] = [PIN_ISR_INIT; 49];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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@ -2172,9 +2123,6 @@ mod chip {
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#[cfg(esp32c3)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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mod chip {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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use core::sync::atomic::AtomicU8;
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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extern crate alloc;
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@ -2196,11 +2144,7 @@ mod chip {
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#[allow(clippy::type_complexity)]
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#[cfg(feature = "alloc")]
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<Box<dyn FnMut()>>>; 22] = [PIN_ISR_INIT; 22];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_INTER: [AtomicU8; 22] = [PIN_INTER_INIT; 22];
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<dyn FnMut()>>; 22] = [PIN_ISR_INIT; 22];
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_NOTIF: [HalIsrNotification; 22] = [PIN_NOTIF_INIT; 22];
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@ -2292,9 +2236,6 @@ mod chip {
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#[cfg(esp32c2)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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mod chip {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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use core::sync::atomic::AtomicU8;
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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extern crate alloc;
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@ -2316,11 +2257,7 @@ mod chip {
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#[allow(clippy::type_complexity)]
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#[cfg(feature = "alloc")]
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<Box<dyn FnMut()>>>; 20] = [PIN_ISR_INIT; 20];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_INTER: [AtomicU8; 20] = [PIN_INTER_INIT; 20];
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<dyn FnMut()>>; 20] = [PIN_ISR_INIT; 20];
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_NOTIF: [HalIsrNotification; 20] = [PIN_NOTIF_INIT; 20];
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@ -2409,9 +2346,6 @@ mod chip {
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#[cfg(esp32h2)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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mod chip {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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use core::sync::atomic::AtomicU8;
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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extern crate alloc;
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@ -2433,11 +2367,7 @@ mod chip {
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#[allow(clippy::type_complexity)]
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#[cfg(feature = "alloc")]
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<Box<dyn FnMut()>>>; 20] = [PIN_ISR_INIT; 20];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_INTER: [AtomicU8; 20] = [PIN_INTER_INIT; 20];
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<dyn FnMut()>>; 20] = [PIN_ISR_INIT; 20];
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#[cfg(not(feature = "riscv-ulp-hal"))]
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pub(crate) static PIN_NOTIF: [HalIsrNotification; 20] = [PIN_NOTIF_INIT; 20];
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@ -2527,9 +2457,6 @@ mod chip {
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#[cfg(any(esp32c5, esp32c6, esp32p4))] // TODO: Implement proper pin layout for esp32c5 and esp32p4
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mod chip {
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#[cfg(not(feature = "riscv-ulp-hal"))]
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use core::sync::atomic::AtomicU8;
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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extern crate alloc;
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@ -2551,11 +2478,7 @@ mod chip {
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#[allow(clippy::type_complexity)]
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#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
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pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<Box<dyn FnMut()>>>; 30] = [PIN_ISR_INIT; 30];
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#[allow(clippy::type_complexity)]
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#[cfg(not(feature = "riscv-ulp-hal"))]
|
||||
pub(crate) static PIN_INTER: [AtomicU8; 30] = [PIN_INTER_INIT; 30];
|
||||
pub(crate) static mut PIN_ISR_HANDLER: [Option<Box<dyn FnMut()>>; 30] = [PIN_ISR_INIT; 30];
|
||||
|
||||
#[allow(clippy::type_complexity)]
|
||||
#[cfg(not(feature = "riscv-ulp-hal"))]
|
||||
|
||||
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Reference in New Issue
Block a user