From 241e97a6fa6b91beface703e9c7e4021a5e5cb4d Mon Sep 17 00:00:00 2001
From: ivmarkov <ivan.markov@gmail.com>
Date: Mon, 6 Dec 2021 10:59:55 +0200
Subject: [PATCH] ULP compatibility for degrading and StatefulPin

---
 Cargo.toml          |  2 +-
 src/gpio.rs         | 16 ++++++++++++++++
 src/ulp/sys/cpu.rs  |  1 +
 src/ulp/sys/gpio.rs | 15 +++++++++++++++
 4 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index 03008ec87..8745b09d1 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "esp-idf-hal"
-version = "0.29.0"
+version = "0.29.1"
 authors = ["sapir <yasapir@gmail.com>", "Ivan Markov <ivan.markov@gmail.com>"]
 edition = "2018"
 resolver = "2"
diff --git a/src/gpio.rs b/src/gpio.rs
index cff3d8e1a..f1388c3a7 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -237,6 +237,7 @@ macro_rules! impl_hal_output_pin {
         }
 
         impl embedded_hal::digital::v2::StatefulOutputPin for $pxi<$mode> {
+            #[cfg(not(feature = "ulp"))]
             fn is_set_high(&self) -> Result<bool, Self::Error> {
                 let pin = $pxi::<$mode>::runtime_pin() as u32;
 
@@ -254,6 +255,11 @@ macro_rules! impl_hal_output_pin {
                 Ok(is_set_high)
             }
 
+            #[cfg(feature = "ulp")]
+            fn is_set_high(&self) -> Result<bool, Self::Error> {
+                Ok(unsafe { gpio_get_output_level($pxi::<$mode>::runtime_pin()) } != 0)
+            }
+
             fn is_set_low(&self) -> Result<bool, Self::Error> {
                 Ok(!self.is_set_high()?)
             }
@@ -524,6 +530,16 @@ macro_rules! impl_rtc {
             fn runtime_pin() -> i32 {
                 $rtc
             }
+
+            /// Degrades a concrete pin (e.g. [`Gpio1`]) to a generic pin
+            /// struct that can also be used with periphals.
+            pub fn degrade(self) -> GpioPin<MODE> {
+                GpioPin::new($pin)
+            }
+
+            pub fn into_unknown(self) -> $pxi<Unknown> {
+                $pxi { _mode: PhantomData }
+            }
         }
 
         impl<MODE> RTCPin for $pxi<MODE>
diff --git a/src/ulp/sys/cpu.rs b/src/ulp/sys/cpu.rs
index b4f400a1d..b1517c8c8 100644
--- a/src/ulp/sys/cpu.rs
+++ b/src/ulp/sys/cpu.rs
@@ -17,6 +17,7 @@ pub fn get_ccount() -> u32 {
     #[allow(unused_assignments)]
     let mut ccount = 0;
 
+    #[allow(deprecated)]
     unsafe {
         llvm_asm!("rdcycle $0" : "=r"(ccount) : : : "volatile");
     }
diff --git a/src/ulp/sys/gpio.rs b/src/ulp/sys/gpio.rs
index 80153e19f..0633a76c8 100644
--- a/src/ulp/sys/gpio.rs
+++ b/src/ulp/sys/gpio.rs
@@ -172,3 +172,18 @@ pub unsafe fn gpio_set_level(gpio_num: i32, level: u8) {
         );
     }
 }
+
+#[inline(always)]
+pub unsafe fn gpio_get_output_level(gpio_num: i32) -> u8 {
+    if (reg_get_field(
+        RTC_GPIO_OUT_W1TS_REG,
+        RTC_GPIO_OUT_DATA_W1TS_S,
+        RTC_GPIO_OUT_DATA_W1TS_V,
+    ) & bit(gpio_num as u32))
+        != 0
+    {
+        1
+    } else {
+        0
+    }
+}