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support uart that defaults to PLL_F80M (#353)

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Erik Tollerud 2024-01-10 02:03:03 -06:00 committed by GitHub
parent e6cafb7e15
commit 33eb2d1057
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1 changed files with 12 additions and 0 deletions
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12
src/uart.rs
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@ -216,6 +216,9 @@ pub mod config {
/// UART source clock from `XTAL`
#[cfg(esp_idf_soc_uart_support_xtal_clk)]
Crystal,
/// UART source clock from `XTAL`
#[cfg(esp_idf_soc_uart_support_pll_f80m_clk)]
PLL_F80M,
/// UART source clock from `REF_TICK`
#[cfg(esp_idf_soc_uart_support_ref_tick)]
RefTick,
@ -242,6 +245,8 @@ pub mod config {
RTC_SCLK => SourceClock::RTC,
#[cfg(esp_idf_soc_uart_support_xtal_clk)]
XTAL_SCLK => SourceClock::Crystal,
#[cfg(esp_idf_soc_uart_support_pll_f80m_clk)]
PLL_F80M => SourceClock::PLL_F80M,
#[cfg(esp_idf_soc_uart_support_ref_tick)]
REF_TICK_SCLK => SourceClock::RefTick,
_ => unreachable!(),
@ -279,6 +284,11 @@ pub mod config {
#[cfg(all(esp_idf_version_major = "4", esp_idf_soc_uart_support_xtal_clk))]
const XTAL_SCLK: uart_sclk_t = uart_sclk_t_UART_SCLK_XTAL;
#[cfg(all(not(esp_idf_version_major = "4"), esp_idf_soc_uart_support_pll_f80m_clk))]
const PLL_F80M_SCLK: uart_sclk_t = soc_periph_uart_clk_src_legacy_t_UART_SCLK_PLL_F80M;
#[cfg(all(esp_idf_version_major = "4", esp_idf_soc_uart_support_pll_f80m_clk))]
const PLL_F80M_SCLK: uart_sclk_t = uart_sclk_t_UART_SCLK_PLL_F80M;
#[cfg(all(not(esp_idf_version_major = "4"), esp_idf_soc_uart_support_ref_tick))]
const REF_TICK_SCLK: uart_sclk_t = soc_periph_uart_clk_src_legacy_t_UART_SCLK_REF_TICK;
#[cfg(all(esp_idf_version_major = "4", esp_idf_soc_uart_support_ref_tick))]
@ -303,6 +313,8 @@ pub mod config {
SourceClock::RTC => RTC_SCLK,
#[cfg(esp_idf_soc_uart_support_xtal_clk)]
SourceClock::Crystal => XTAL_SCLK,
#[cfg(esp_idf_soc_uart_support_pll_f80m_clk)]
SourceClock::PLL_F80M => PLL_F80M_SCLK,
#[cfg(esp_idf_soc_uart_support_ref_tick)]
SourceClock::RefTick => REF_TICK_SCLK,
}