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https://github.com/esp-rs/esp-idf-hal.git
synced 2025-09-26 20:00:35 +00:00
Remove link_section from places where it did not have any effect anyway
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@ -18,7 +18,6 @@ pub enum Core {
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impl Core {
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#[inline(always)]
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#[link_section = ".iram1.cpu_core"]
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pub fn is_active(&self) -> bool {
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*self == core()
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}
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@ -208,7 +208,6 @@ fn exit(cs: &IsrCriticalSection) {
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impl IsrCriticalSection {
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/// Constructs a new `IsrCriticalSection` instance
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#[inline(always)]
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#[link_section = ".iram1.interrupt_cs_new"]
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pub const fn new() -> Self {
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#[cfg(any(esp32, esp32s2, esp32s3, esp32p4))]
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let mux = core::cell::UnsafeCell::new(portMUX_TYPE {
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@ -241,7 +240,6 @@ impl IsrCriticalSection {
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///
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/// For more information, refer to https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/freertos-smp.html#critical-sections
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#[inline(always)]
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#[link_section = ".iram1.interrupt_cs_enter"]
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pub fn enter(&self) -> IsrCriticalSectionGuard<'_> {
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enter(self);
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@ -251,7 +249,6 @@ impl IsrCriticalSection {
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impl Default for IsrCriticalSection {
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#[inline(always)]
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#[link_section = ".iram1.interrupt_cs_default"]
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fn default() -> Self {
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Self::new()
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}
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@ -271,7 +268,6 @@ impl Drop for IsrCriticalSectionGuard<'_> {
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/// interrupts for the core will be re-enabled only when the last guard that
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/// disabled interrupts for the concrete core is dropped.
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#[inline(always)]
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#[link_section = ".iram1.interrupt_csg_drop"]
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fn drop(&mut self) {
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exit(self.0);
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}
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10
src/task.rs
10
src/task.rs
@ -523,13 +523,11 @@ fn exit(cs: &CriticalSection) {
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impl CriticalSection {
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/// Constructs a new `CriticalSection` instance
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#[inline(always)]
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#[link_section = ".iram1.cs_new"]
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pub const fn new() -> Self {
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Self(Cell::new(None), AtomicBool::new(false))
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}
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#[inline(always)]
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#[link_section = ".iram1.cs_enter"]
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pub fn enter(&self) -> CriticalSectionGuard<'_> {
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enter(self);
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@ -549,7 +547,6 @@ impl Drop for CriticalSection {
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impl Default for CriticalSection {
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#[inline(always)]
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#[link_section = ".iram1.cs_default"]
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fn default() -> Self {
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Self::new()
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}
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@ -562,7 +559,6 @@ pub struct CriticalSectionGuard<'a>(&'a CriticalSection);
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impl Drop for CriticalSectionGuard<'_> {
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#[inline(always)]
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#[link_section = ".iram1.csg_drop"]
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fn drop(&mut self) {
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exit(self.0);
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}
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@ -1035,7 +1031,6 @@ pub mod queue {
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/// Retrieves the underlying FreeRTOS handle.
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#[inline]
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#[link_section = "iram1.queue_as_raw"]
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pub fn as_raw(&self) -> sys::QueueHandle_t {
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self.ptr
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}
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@ -1059,7 +1054,6 @@ pub mod queue {
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/// In non-ISR contexts, the function will always return `false`.
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/// In this case the interrupt should call [`crate::task::do_yield`].
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#[inline]
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#[link_section = "iram1.queue_send_back"]
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pub fn send_back(&self, item: T, timeout: TickType_t) -> Result<bool, EspError> {
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self.send_generic(item, timeout, 0)
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}
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@ -1085,7 +1079,6 @@ pub mod queue {
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/// In non-ISR contexts, the function will always return `false`.
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/// In this case the interrupt should call [`crate::task::do_yield`].
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#[inline]
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#[link_section = "iram1.queue_send_front"]
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pub fn send_front(&self, item: T, timeout: TickType_t) -> Result<bool, EspError> {
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self.send_generic(item, timeout, 1)
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}
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@ -1110,7 +1103,6 @@ pub mod queue {
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/// In non-ISR contexts, the function will always return `false`.
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/// In this case the interrupt should call [`crate::task::do_yield`].
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#[inline]
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#[link_section = "iram1.queue_send_generic"]
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fn send_generic(
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&self,
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item: T,
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@ -1163,7 +1155,6 @@ pub mod queue {
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/// In this case the interrupt should call [`crate::task::do_yield`].
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/// In non-ISR contexts, the function will always return `false`.
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#[inline]
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#[link_section = "iram1.queue_recv_front"]
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pub fn recv_front(&self, timeout: TickType_t) -> Option<(T, bool)> {
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let mut buf = MaybeUninit::uninit();
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let mut hp_task_awoken = false as i32;
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@ -1205,7 +1196,6 @@ pub mod queue {
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/// a higher priority task was awoken since we don't free
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/// up space in the queue and thus cannot unblock anyone.
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#[inline]
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#[link_section = "iram1.queue_peek_front"]
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pub fn peek_front(&self, timeout: TickType_t) -> Option<T> {
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let mut buf = MaybeUninit::uninit();
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