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esp32c6 can use the PLL160M clock actually

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This commit is contained in:
ivmarkov 2023-10-18 11:35:19 +00:00
parent fcfd0779e2
commit 83674fbc90
2 changed files with 5 additions and 5 deletions
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2
CHANGELOG.md
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@ -7,7 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
## [0.42.1] - 2023-10-18
* Fix ambiguous name error #325 - a compilation issue when the NimBLE component is enabled in `esp-idf-sys`
* Fix compilation issues of the I2S driver for esp32h2, esp32c2 and esp32c6
* Fix compilation issues of the I2S driver for esp32h2 and esp32c2
* Fix compilation issues of the ADC drivers when the ESP IDF `esp_adc` component is not enabled
* Fix compilation issues of the GPIO driver for esp32c6

8
src/i2s.rs
View File

@ -95,7 +95,7 @@ pub mod config {
#[derive(Clone, Copy, Debug, Eq, PartialEq, Default)]
pub enum ClockSource {
/// Use PLL_F160M as the source clock
#[cfg(not(any(esp32h2, esp32c2, esp32c6)))]
#[cfg(not(any(esp32h2, esp32c2)))]
#[default]
Pll160M,
@ -105,7 +105,7 @@ pub mod config {
Pll60M,
/// Use PLL_F64M as the source clock
#[cfg(any(esp32h2, esp32c6))]
#[cfg(esp32h2)]
#[default]
Pll64M,
@ -119,7 +119,7 @@ pub mod config {
#[allow(clippy::unnecessary_cast)]
pub(super) fn as_sdk(&self) -> i2s_clock_src_t {
match self {
#[cfg(not(any(esp32h2, esp32c2, esp32c6)))]
#[cfg(not(any(esp32h2, esp32c2)))]
Self::Pll160M => core::convert::TryInto::try_into(
esp_idf_sys::soc_module_clk_t_SOC_MOD_CLK_PLL_F160M,
)
@ -129,7 +129,7 @@ pub mod config {
esp_idf_sys::soc_module_clk_t_SOC_MOD_CLK_PLL_F60M,
)
.unwrap(),
#[cfg(any(esp32h2, esp32c6))]
#[cfg(esp32h2)]
Self::Pll64M => core::convert::TryInto::try_into(
esp_idf_sys::soc_module_clk_t_SOC_MOD_CLK_PLL_F64M,
)