From e79df5a8736886b9102051786c7f5ae90688dcd0 Mon Sep 17 00:00:00 2001 From: ivmarkov Date: Thu, 18 Jan 2024 20:12:27 +0000 Subject: [PATCH] Get rid of the riscv-ulp-hal feature --- .github/workflows/ci.yml | 9 +- CHANGELOG.md | 1 + Cargo.toml | 6 +- build.rs | 22 -- examples/pcnt_rotary_encoder.rs | 15 +- src/adc.rs | 31 +- src/gpio.rs | 547 ++++---------------------------- src/lib.rs | 110 +------ src/peripherals.rs | 288 ++++------------- src/riscv_ulp_hal.rs | 12 - src/riscv_ulp_hal/delay.rs | 57 ---- src/riscv_ulp_hal/pac.rs | 66 ---- src/riscv_ulp_hal/reg.rs | 173 ---------- src/riscv_ulp_hal/start.rs | 179 ----------- src/riscv_ulp_hal/sys.rs | 28 -- src/riscv_ulp_hal/sys/cpu.rs | 71 ----- src/riscv_ulp_hal/sys/gpio.rs | 204 ------------ src/sys.rs | 4 - src/task.rs | 15 +- 19 files changed, 144 insertions(+), 1694 deletions(-) delete mode 100644 src/riscv_ulp_hal.rs delete mode 100644 src/riscv_ulp_hal/delay.rs delete mode 100644 src/riscv_ulp_hal/pac.rs delete mode 100644 src/riscv_ulp_hal/reg.rs delete mode 100644 src/riscv_ulp_hal/start.rs delete mode 100644 src/riscv_ulp_hal/sys.rs delete mode 100644 src/riscv_ulp_hal/sys/cpu.rs delete mode 100644 src/riscv_ulp_hal/sys/gpio.rs diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8ddbd086f..60495228e 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -65,24 +65,19 @@ jobs: RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}" run: cargo build --target ${{ matrix.target }} --features nightly,critical-section,embassy-sync -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort - - name: Build | RISCV-ULP-HAL feature - env: - ESP_IDF_VERSION: ${{ matrix.idf-version }} - run: cargo build --features riscv-ulp-hal --no-default-features --target riscv32imc-unknown-none-elf -Zbuild-std=core,panic_abort -Zbuild-std-features=panic_immediate_abort - - name: Build | Compile, no_std env: ESP_IDF_VERSION: ${{ matrix.idf-version }} ESP_IDF_SDKCONFIG_DEFAULTS: "${{ github.workspace }}/.github/configs/sdkconfig.defaults" RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}" - run: cargo build --features esp-idf-sys --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort + run: cargo build --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort - name: Build | Compile, no_std, alloc env: ESP_IDF_VERSION: ${{ matrix.idf-version }} ESP_IDF_SDKCONFIG_DEFAULTS: "${{ github.workspace }}/.github/configs/sdkconfig.defaults" RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}" - run: cargo build --features alloc,esp-idf-sys --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort + run: cargo build --features alloc --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort - name: Setup | ldproxy if: matrix.target == 'riscv32imc-esp-espidf' diff --git a/CHANGELOG.md b/CHANGELOG.md index bb074aa4a..22ee79e03 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). ## [?.??.?] - ????-??-?? +* Breaking change: feature `riscv-ulp-hal` (and consequently, feature `esp-idf-sys`) is now removed. Use the [esp-ulp-riscv-hal](https://github.com/esp-rs/esp-hal/tree/main/esp-ulp-riscv-hal) crate instead * MSRV 1.75; remove the nightly feature flag from all async trait implementations * Update public dependencies `e-hal` to 1.0.0 and `embassy-sync` to 0.5 and private dependency `heapless` to 0.8 * Allow `cargo check --all-features` to work correctly (there used to be a build error when both the `esp-idf-sys` and the `riscv-ulp-hal` features were enabled) diff --git a/Cargo.toml b/Cargo.toml index fa6c952b8..4e59a3843 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,8 +23,6 @@ default = ["std", "binstart"] std = ["alloc", "esp-idf-sys/std"] alloc = [] nightly = [] -esp-idf-sys = ["dep:esp-idf-sys", "atomic-waker"] -riscv-ulp-hal = [] wake-from-isr = [] # Only enable if you plan to use the `edge-executor` crate embassy-sync = [] # For now, the dependecy on the `embassy-sync` crate is non-optional, but this might change in future @@ -45,13 +43,13 @@ embedded-hal-nb = "1" embedded-hal-async = "1" embedded-io = "0.6" embedded-io-async = "0.6" -esp-idf-sys = { version = "0.33.7", optional = true, default-features = false } +esp-idf-sys = { version = "0.33.7", default-features = false } critical-section = { version = "1.1.1", optional = true } heapless = "0.8" num_enum = { version = "0.7", default-features = false } enumset = { version = "1", default-features = false } log = { version = "0.4", default-features = false } -atomic-waker = { version = "1.1.1", optional = true, default-features = false } +atomic-waker = { version = "1.1.1", default-features = false } embassy-sync = { version = "0.5" } [build-dependencies] diff --git a/build.rs b/build.rs index 2a36fa563..f0f0a39dd 100644 --- a/build.rs +++ b/build.rs @@ -1,26 +1,4 @@ -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] fn main() { embuild::espidf::sysenv::relay(); embuild::espidf::sysenv::output(); // Only necessary for building the examples } - -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -fn main() { - println!("cargo:rustc-cfg=esp32s2"); - - let riscv_ulp_dir = std::env::current_dir().unwrap().join("riscv-ulp"); - println!("cargo:rustc-link-search={}", riscv_ulp_dir.display()); - - println!( - "cargo:rerun-if-changed={}", - riscv_ulp_dir.join("libriscv_ulp_start.a").display() - ); - println!( - "cargo:rerun-if-changed={}", - riscv_ulp_dir.join("riscv_ulp_link_base.x").display() - ); - println!( - "cargo:rerun-if-changed={}", - riscv_ulp_dir.join("riscv_ulp_link_default.x").display() - ); -} diff --git a/examples/pcnt_rotary_encoder.rs b/examples/pcnt_rotary_encoder.rs index efd715c1f..446e0bc34 100644 --- a/examples/pcnt_rotary_encoder.rs +++ b/examples/pcnt_rotary_encoder.rs @@ -6,10 +6,7 @@ //! threshold and track how much that accounts for and provide an i32 value result //! -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) -))] +#[cfg(any(esp32, esp32s2, esp32s3))] fn main() -> anyhow::Result<()> { use anyhow::Context; use encoder::Encoder; @@ -38,10 +35,7 @@ fn main() -> anyhow::Result<()> { } } -#[cfg(not(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) -)))] +#[cfg(not(any(esp32, esp32s2, esp32s3)))] fn main() { use esp_idf_hal::delay::FreeRtos; println!("pcnt peripheral not supported on this device!"); @@ -50,10 +44,7 @@ fn main() { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) -))] +#[cfg(any(esp32, esp32s2, esp32s3))] // esp-idf encoder implementation using v4 pcnt api mod encoder { use std::cmp::min; diff --git a/src/adc.rs b/src/adc.rs index 6d14921b0..b79427689 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,20 +1,12 @@ -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -use crate::riscv_ulp_hal::sys::*; - -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::gpio::ADCPin; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::peripheral::{Peripheral, PeripheralRef}; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub type AdcConfig = config::Config; #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), not(esp_idf_version_major = "4"), not(esp32c2), esp_idf_comp_esp_adc_enabled @@ -30,7 +22,6 @@ pub trait Adc: Send { } // NOTE: Will be changed to an enum once C-style enums are usable as const generics -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod attenuation { pub use esp_idf_sys::{ adc_atten_t, adc_atten_t_ADC_ATTEN_DB_0, adc_atten_t_ADC_ATTEN_DB_11, @@ -44,7 +35,6 @@ pub mod attenuation { } /// ADC configuration -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod config { use esp_idf_sys::*; @@ -119,12 +109,10 @@ pub mod config { } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub struct AdcChannelDriver<'d, const A: adc_atten_t, T: ADCPin> { pin: PeripheralRef<'d, T>, } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl<'d, const A: adc_atten_t, T: ADCPin> AdcChannelDriver<'d, A, T> { pub fn new(pin: impl Peripheral

+ 'd) -> Result { crate::into_ref!(pin); @@ -151,7 +139,6 @@ impl<'d, const A: adc_atten_t, T: ADCPin> AdcChannelDriver<'d, A, T> { } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl<'d, const A: adc_atten_t, T: ADCPin> embedded_hal_0_2::adc::Channel for AdcChannelDriver<'d, A, T> { @@ -162,7 +149,6 @@ impl<'d, const A: adc_atten_t, T: ADCPin> embedded_hal_0_2::adc::Channel } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub struct AdcDriver<'d, ADC: Adc> { _adc: PeripheralRef<'d, ADC>, #[allow(dead_code)] @@ -175,10 +161,8 @@ pub struct AdcDriver<'d, ADC: Adc> { Option<[Option; adc_atten_t_ADC_ATTEN_DB_11 as usize + 1]>, } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] unsafe impl<'d, ADC: Adc> Send for AdcDriver<'d, ADC> {} -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl<'d, ADC: Adc> AdcDriver<'d, ADC> { #[cfg(all( esp32, @@ -403,7 +387,6 @@ impl<'d, ADC: Adc> AdcDriver<'d, ADC> { } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl<'d, 'c, const A: adc_atten_t, T> embedded_hal_0_2::adc::OneShot> for AdcDriver<'d, T::Adc> @@ -418,11 +401,7 @@ where } } -#[cfg(all( - esp32, - esp_idf_version_major = "4", - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) -))] +#[cfg(all(esp32, esp_idf_version_major = "4"))] impl<'d> embedded_hal_0_2::adc::OneShot for AdcDriver<'d, ADC1> { @@ -433,7 +412,6 @@ impl<'d> embedded_hal_0_2::adc::OneShot } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] fn to_nb_err(err: EspError) -> nb::Error { if err.code() == ESP_ERR_INVALID_STATE { nb::Error::WouldBlock @@ -459,11 +437,7 @@ impl_adc!(ADC1: adc_unit_t_ADC_UNIT_1); #[cfg(not(any(esp32c2, esp32h2, esp32c5, esp32c6, esp32p4)))] // TODO: Check for esp32c5 and esp32p4 impl_adc!(ADC2: adc_unit_t_ADC_UNIT_2); -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(esp_idf_version_major = "4"), - esp_idf_comp_esp_adc_enabled -))] +#[cfg(all(not(esp_idf_version_major = "4"), esp_idf_comp_esp_adc_enabled))] pub mod oneshot { use core::borrow::Borrow; @@ -791,7 +765,6 @@ pub mod oneshot { } #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), not(esp_idf_version_major = "4"), not(esp32c2), esp_idf_comp_esp_adc_enabled diff --git a/src/gpio.rs b/src/gpio.rs index 4ea9d807e..acee0c053 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -2,18 +2,11 @@ use core::marker::PhantomData; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" -))] +#[cfg(feature = "alloc")] extern crate alloc; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -use crate::riscv_ulp_hal::sys::*; - use crate::adc::Adc; use crate::peripheral::{Peripheral, PeripheralRef}; @@ -209,7 +202,6 @@ impl From for AnyOutputPin { } /// Interrupt types -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] #[derive(Debug, Eq, PartialEq, Copy, Clone)] pub enum InterruptType { PosEdge, @@ -219,7 +211,6 @@ pub enum InterruptType { HighLevel, } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl From for gpio_int_type_t { fn from(interrupt_type: InterruptType) -> gpio_int_type_t { match interrupt_type { @@ -232,7 +223,6 @@ impl From for gpio_int_type_t { } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl From for u8 { fn from(interrupt_type: InterruptType) -> u8 { let int_type: gpio_int_type_t = interrupt_type.into(); @@ -242,7 +232,6 @@ impl From for u8 { } /// Drive strength (values are approximates) -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] #[derive(Debug, Eq, PartialEq, Copy, Clone)] pub enum DriveStrength { I5mA = 0, @@ -251,7 +240,6 @@ pub enum DriveStrength { I40mA = 3, } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl From for gpio_drive_cap_t { fn from(strength: DriveStrength) -> gpio_drive_cap_t { match strength { @@ -263,7 +251,6 @@ impl From for gpio_drive_cap_t { } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl From for DriveStrength { #[allow(non_upper_case_globals)] fn from(cap: gpio_drive_cap_t) -> DriveStrength { @@ -371,10 +358,7 @@ impl From for embedded_hal::digital::PinState { pub trait GPIOMode {} -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub trait RTCMode {} pub trait InputMode { @@ -389,25 +373,13 @@ pub struct Disabled; pub struct Input; pub struct Output; pub struct InputOutput; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub struct RtcDisabled; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub struct RtcInput; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub struct RtcOutput; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub struct RtcInputOutput; impl InputMode for Input { @@ -431,60 +403,36 @@ impl GPIOMode for Input {} impl GPIOMode for InputOutput {} impl GPIOMode for Output {} -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl InputMode for RtcInput { const RTC: bool = true; } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl InputMode for RtcInputOutput { const RTC: bool = true; } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl OutputMode for RtcOutput { const RTC: bool = true; } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl OutputMode for RtcInputOutput { const RTC: bool = true; } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl RTCMode for RtcDisabled {} -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl RTCMode for RtcInput {} -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl RTCMode for RtcInputOutput {} -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl RTCMode for RtcOutput {} /// A driver for a GPIO pin. @@ -584,10 +532,7 @@ impl<'d, T: OutputPin> PinDriver<'d, T, Output> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl<'d, T: Pin + RTCPin> PinDriver<'d, T, RtcDisabled> { /// Creates the driver for a pin in disabled state. #[inline] @@ -602,10 +547,7 @@ impl<'d, T: Pin + RTCPin> PinDriver<'d, T, RtcDisabled> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl<'d, T: InputPin + RTCPin> PinDriver<'d, T, RtcInput> { /// Creates the driver for a pin in RTC input state. #[inline] @@ -620,10 +562,7 @@ impl<'d, T: InputPin + RTCPin> PinDriver<'d, T, RtcInput> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl<'d, T: InputPin + OutputPin + RTCPin> PinDriver<'d, T, RtcInputOutput> { /// Creates the driver for a pin in RTC input-output state. #[inline] @@ -638,10 +577,7 @@ impl<'d, T: InputPin + OutputPin + RTCPin> PinDriver<'d, T, RtcInputOutput> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl<'d, T: InputPin + OutputPin + RTCPin> PinDriver<'d, T, RtcInputOutput> { /// Creates the driver for a pin in RTC input-output open-drain state. #[inline] @@ -656,10 +592,7 @@ impl<'d, T: InputPin + OutputPin + RTCPin> PinDriver<'d, T, RtcInputOutput> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl<'d, T: OutputPin + RTCPin> PinDriver<'d, T, RtcOutput> { /// Creates the driver for a pin in RTC output state. #[inline] @@ -674,10 +607,7 @@ impl<'d, T: OutputPin + RTCPin> PinDriver<'d, T, RtcOutput> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) -))] +#[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] impl<'d, T: OutputPin + RTCPin> PinDriver<'d, T, RtcOutput> { /// Creates the driver for a pin in RTC output open-drain state. #[inline] @@ -755,10 +685,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// Put the pin into RTC disabled mode. #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub fn into_rtc_disabled(self) -> Result, EspError> where T: RTCPin, @@ -768,10 +695,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// Put the pin into RTC input mode. #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub fn into_rtc_input(self) -> Result, EspError> where T: InputPin + RTCPin, @@ -786,10 +710,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// it to high, in which case you can read the input to figure out whether another device /// is driving the line low. #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub fn into_rtc_input_output(self) -> Result, EspError> where T: InputPin + OutputPin + RTCPin, @@ -804,10 +725,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// it to high, in which case you can read the input to figure out whether another device /// is driving the line low. #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub fn into_rtc_input_output_od(self) -> Result, EspError> where T: InputPin + OutputPin + RTCPin, @@ -817,10 +735,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// Put the pin into RTC output mode. #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub fn into_rtc_output(self) -> Result, EspError> where T: OutputPin + RTCPin, @@ -830,10 +745,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// Put the pin into RTC output Open Drain mode. #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] pub fn into_rtc_output_od(self) -> Result, EspError> where T: OutputPin + RTCPin, @@ -861,10 +773,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } #[inline] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] fn into_rtc_mode(mut self, mode: rtc_gpio_mode_t) -> Result, EspError> where T: RTCPin, @@ -873,10 +782,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { drop(self); - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] { esp!(unsafe { rtc_gpio_init(pin.pin()) })?; esp!(unsafe { rtc_gpio_set_direction(pin.pin(), mode) })?; @@ -889,7 +795,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } #[inline] - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn get_drive_strength(&self) -> Result where MODE: OutputMode, @@ -897,16 +802,10 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { let mut cap: gpio_drive_cap_t = 0; if MODE::RTC { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] esp!(unsafe { rtc_gpio_get_drive_capability(self.pin.pin(), &mut cap) })?; - #[cfg(any( - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")), - any(esp32c3, esp32c2, esp32h2, esp32c5) - ))] + #[cfg(any(esp32c3, esp32c2, esp32h2, esp32c5))] unreachable!(); } else { esp!(unsafe { gpio_get_drive_capability(self.pin.pin(), &mut cap) })?; @@ -916,22 +815,15 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } #[inline] - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn set_drive_strength(&mut self, strength: DriveStrength) -> Result<(), EspError> where MODE: OutputMode, { if MODE::RTC { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] esp!(unsafe { rtc_gpio_set_drive_capability(self.pin.pin(), strength.into()) })?; - #[cfg(any( - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")), - any(esp32c3, esp32c2, esp32h2, esp32c5) - ))] + #[cfg(any(esp32c3, esp32c2, esp32h2, esp32c5))] unreachable!(); } else { esp!(unsafe { gpio_set_drive_capability(self.pin.pin(), strength.into()) })?; @@ -964,10 +856,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { let res; if MODE::RTC { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] { res = if unsafe { rtc_gpio_get_level(self.pin.pin()) } != 0 { Level::High @@ -976,10 +865,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { }; } - #[cfg(any( - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")), - any(esp32c3, esp32c2, esp32h2, esp32c5) - ))] + #[cfg(any(esp32c3, esp32c2, esp32h2, esp32c5))] unreachable!(); } else if unsafe { gpio_get_level(self.pin.pin()) } != 0 { res = Level::High; @@ -1009,7 +895,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// What level output is set to #[inline] - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] fn get_output_level(&self) -> Level where MODE: OutputMode, @@ -1036,20 +921,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } } - /// What level output is set to - #[inline] - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - fn get_output_level(&self) -> Level - where - MODE: OutputMode, - { - if unsafe { gpio_get_output_level(self.pin.pin()) } != 0 { - Level::High - } else { - Level::Low - } - } - #[inline] pub fn set_high(&mut self) -> Result<(), EspError> where @@ -1078,16 +949,10 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { }; if MODE::RTC { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] esp!(unsafe { rtc_gpio_set_level(self.pin.pin(), on) })?; - #[cfg(any( - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")), - any(esp32c3, esp32c2, esp32h2, esp32c5) - ))] + #[cfg(any(esp32c3, esp32c2, esp32h2, esp32c5))] unreachable!(); } else { esp!(unsafe { gpio_set_level(self.pin.pin(), on) })?; @@ -1115,10 +980,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { MODE: InputMode, { if MODE::RTC { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(any(esp32c3, esp32c2, esp32h2, esp32c5)) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32h2, esp32c5)))] unsafe { match pull { Pull::Down => { @@ -1140,10 +1002,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } } - #[cfg(any( - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")), - any(esp32c3, esp32c2, esp32h2, esp32c5) - ))] + #[cfg(any(esp32c3, esp32c2, esp32h2, esp32c5))] unreachable!(); } else { esp!(unsafe { gpio_set_pull_mode(self.pin.pin(), pull.into()) })?; @@ -1164,10 +1023,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// /// Care should be taken not to call STD, libc or FreeRTOS APIs (except for a few allowed ones) /// in the callback passed to this function, as it is executed in an ISR context. - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] pub unsafe fn subscribe( &mut self, callback: F, @@ -1212,10 +1068,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// /// This "local borrowing" will only be possible to express in a safe way once/if `!Leak` types /// are introduced to Rust (i.e. the impossibility to "forget" a type and thus not call its destructor). - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] pub unsafe fn subscribe_nonstatic( &mut self, callback: F, @@ -1226,10 +1079,7 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { self.internal_subscribe(callback) } - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] fn internal_subscribe(&mut self, callback: impl FnMut() + Send + 'd) -> Result<(), EspError> where MODE: InputMode, @@ -1246,7 +1096,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { Ok(()) } - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn unsubscribe(&mut self) -> Result<(), EspError> where MODE: InputMode, @@ -1266,7 +1115,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { /// /// Therefore - to continue receiving ISR interrupts - user needs to call `enable_interrupt` /// - **from a non-ISR context** - after each successful interrupt triggering. - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn enable_interrupt(&mut self) -> Result<(), EspError> where MODE: InputMode, @@ -1282,7 +1130,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } } - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn disable_interrupt(&mut self) -> Result<(), EspError> where MODE: InputMode, @@ -1296,7 +1143,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { Ok(()) } - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn set_interrupt_type(&mut self, interrupt_type: InterruptType) -> Result<(), EspError> where MODE: InputMode, @@ -1306,7 +1152,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { Ok(()) } - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] unsafe extern "C" fn handle_isr(user_ctx: *mut core::ffi::c_void) { let pin = user_ctx as u32; @@ -1326,7 +1171,6 @@ impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> { } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl PinDriver<'_, T, MODE> { pub async fn wait_for(&mut self, interrupt_type: InterruptType) -> Result<(), EspError> { self.disable_interrupt()?; @@ -1521,7 +1365,6 @@ where } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] impl embedded_hal_async::digital::Wait for PinDriver<'_, T, MODE> { async fn wait_for_high(&mut self) -> Result<(), GpioError> { self.wait_for_high().await?; @@ -1554,17 +1397,13 @@ impl embedded_hal_async::digital::Wait for PinDriver<'_ } } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] static ISR_ALLOC_FLAGS: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0); -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] static ISR_SERVICE_ENABLED: core::sync::atomic::AtomicBool = core::sync::atomic::AtomicBool::new(false); -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] static ISR_SERVICE_ENABLED_CS: crate::task::CriticalSection = crate::task::CriticalSection::new(); -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn init_isr_alloc_flags(flags: enumset::EnumSet) { ISR_ALLOC_FLAGS.store( crate::interrupt::InterruptType::to_native(flags), @@ -1572,7 +1411,6 @@ pub fn init_isr_alloc_flags(flags: enumset::EnumSet Result<(), EspError> { use core::sync::atomic::Ordering; @@ -1589,7 +1427,6 @@ pub fn enable_isr_service() -> Result<(), EspError> { Ok(()) } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) unsafe fn rtc_reset_pin(pin: i32) -> Result<(), EspError> { reset_pin(pin, gpio_mode_t_GPIO_MODE_DISABLE)?; @@ -1600,23 +1437,14 @@ pub(crate) unsafe fn rtc_reset_pin(pin: i32) -> Result<(), EspError> { } unsafe fn reset_pin(_pin: i32, _mode: gpio_mode_t) -> Result<(), EspError> { - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] - let res = { - unsubscribe_pin(_pin)?; + unsubscribe_pin(_pin)?; - esp!(gpio_reset_pin(_pin))?; - esp!(gpio_set_direction(_pin, _mode))?; + esp!(gpio_reset_pin(_pin))?; + esp!(gpio_set_direction(_pin, _mode))?; - Ok(()) - }; - - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - let res = Ok(()); - - res + Ok(()) } -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] unsafe fn unsubscribe_pin(pin: i32) -> Result<(), EspError> { use core::sync::atomic::Ordering; @@ -1634,14 +1462,10 @@ unsafe fn unsubscribe_pin(pin: i32) -> Result<(), EspError> { Ok(()) } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" -))] +#[cfg(feature = "alloc")] #[allow(clippy::declare_interior_mutable_const)] // OK because this is only used as an array initializer const PIN_ISR_INIT: Option> = None; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] #[allow(clippy::declare_interior_mutable_const)] // OK because this is only used as an array initializer const PIN_NOTIF_INIT: crate::interrupt::asynch::HalIsrNotification = crate::interrupt::asynch::HalIsrNotification::new(); @@ -1779,25 +1603,14 @@ macro_rules! pin { #[cfg(esp32)] mod chip { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] extern crate alloc; - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] use alloc::boxed::Box; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - use crate::riscv_ulp_hal::sys::*; - - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::interrupt::asynch::HalIsrNotification; use crate::adc::{ADC1, ADC2}; @@ -1805,57 +1618,37 @@ mod chip { use super::*; #[allow(clippy::type_complexity)] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] pub(crate) static mut PIN_ISR_HANDLER: [Option>; 40] = [PIN_ISR_INIT; 40]; #[allow(clippy::type_complexity)] - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) static PIN_NOTIF: [HalIsrNotification; 40] = [PIN_NOTIF_INIT; 40]; // NOTE: Gpio26 - Gpio32 are used by SPI0/SPI1 for external PSRAM/SPI Flash and // are not recommended for other uses pin!(Gpio0:0, IO, RTC:11, ADC2:1, NODAC:0, TOUCH:1); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio1:1, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pin!(Gpio2:2, IO, RTC:12, ADC2:2, NODAC:0, TOUCH:2); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio3:3, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pin!(Gpio4:4, IO, RTC:10, ADC2:0, NODAC:0, TOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio5:5, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio6:6, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio7:7, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio8:8, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio9:9, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio10:10, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio11:11, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pin!(Gpio12:12, IO, RTC:15, ADC2:5, NODAC:0, TOUCH:5); pin!(Gpio13:13, IO, RTC:14, ADC2:4, NODAC:0, TOUCH:4); pin!(Gpio14:14, IO, RTC:16, ADC2:6, NODAC:0, TOUCH:6); pin!(Gpio15:15, IO, RTC:13, ADC2:3, NODAC:0, TOUCH:3); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio16:16, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio17:17, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio18:18, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio19:19, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio21:21, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio22:22, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio23:23, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pin!(Gpio25:25, IO, RTC:6, ADC2:8, DAC:1, NOTOUCH:0); pin!(Gpio26:26, IO, RTC:7, ADC2:9, DAC:2, NOTOUCH:0); @@ -1871,43 +1664,27 @@ mod chip { pub struct Pins { pub gpio0: Gpio0, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio1: Gpio1, pub gpio2: Gpio2, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio3: Gpio3, pub gpio4: Gpio4, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio5: Gpio5, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio6: Gpio6, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio7: Gpio7, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio8: Gpio8, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio9: Gpio9, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio10: Gpio10, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio11: Gpio11, pub gpio12: Gpio12, pub gpio13: Gpio13, pub gpio14: Gpio14, pub gpio15: Gpio15, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio16: Gpio16, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio17: Gpio17, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio18: Gpio18, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio19: Gpio19, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio21: Gpio21, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio22: Gpio22, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio23: Gpio23, pub gpio25: Gpio25, pub gpio26: Gpio26, @@ -1930,43 +1707,27 @@ mod chip { pub unsafe fn new() -> Self { Self { gpio0: Gpio0::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio1: Gpio1::new(), gpio2: Gpio2::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio3: Gpio3::new(), gpio4: Gpio4::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio5: Gpio5::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio6: Gpio6::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio7: Gpio7::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio8: Gpio8::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio9: Gpio9::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio10: Gpio10::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio11: Gpio11::new(), gpio12: Gpio12::new(), gpio13: Gpio13::new(), gpio14: Gpio14::new(), gpio15: Gpio15::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio16: Gpio16::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio17: Gpio17::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio18: Gpio18::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio19: Gpio19::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio21: Gpio21::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio22: Gpio22::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio23: Gpio23::new(), gpio25: Gpio25::new(), gpio26: Gpio26::new(), @@ -1986,25 +1747,14 @@ mod chip { #[cfg(any(esp32s2, esp32s3))] mod chip { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] extern crate alloc; - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] use alloc::boxed::Box; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - use crate::riscv_ulp_hal::sys::*; - - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::interrupt::asynch::HalIsrNotification; use crate::adc::{ADC1, ADC2}; @@ -2012,15 +1762,11 @@ mod chip { use super::*; #[allow(clippy::type_complexity)] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] pub(crate) static mut PIN_ISR_HANDLER: [Option>; 49] = [PIN_ISR_INIT; 49]; #[allow(clippy::type_complexity)] - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) static PIN_NOTIF: [HalIsrNotification; 49] = [PIN_NOTIF_INIT; 49]; // NOTE: Gpio26 - Gpio32 (and Gpio33 - Gpio37 if using Octal RAM/Flash) are used @@ -2054,65 +1800,33 @@ mod chip { pin!(Gpio19:19, IO, RTC:19, ADC2:8, NODAC:0, NOTOUCH:0); pin!(Gpio20:20, IO, RTC:20, ADC2:9, NODAC:0, NOTOUCH:0); pin!(Gpio21:21, IO, RTC:21, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio26:26, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio27:27, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio28:28, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio29:29, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio30:30, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio31:31, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio32:32, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio33:33, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio34:34, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio35:35, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio36:36, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio37:37, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio38:38, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio39:39, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio40:40, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio41:41, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio42:42, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio43:43, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio44:44, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio45:45, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(all( - esp32s2, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s2)] pin!(Gpio46:46, Input, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] pin!(Gpio46:46, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] pin!(Gpio47:47, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] pin!(Gpio48:48, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pub struct Pins { @@ -2138,57 +1852,30 @@ mod chip { pub gpio19: Gpio19, pub gpio20: Gpio20, pub gpio21: Gpio21, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio26: Gpio26, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio27: Gpio27, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio28: Gpio28, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio29: Gpio29, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio30: Gpio30, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio31: Gpio31, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio32: Gpio32, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio33: Gpio33, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio34: Gpio34, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio35: Gpio35, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio36: Gpio36, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio37: Gpio37, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio38: Gpio38, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio39: Gpio39, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio40: Gpio40, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio41: Gpio41, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio42: Gpio42, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio43: Gpio43, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio44: Gpio44, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio45: Gpio45, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio46: Gpio46, - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] pub gpio47: Gpio47, - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] pub gpio48: Gpio48, } @@ -2221,57 +1908,30 @@ mod chip { gpio19: Gpio19::new(), gpio20: Gpio20::new(), gpio21: Gpio21::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio26: Gpio26::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio27: Gpio27::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio28: Gpio28::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio29: Gpio29::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio30: Gpio30::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio31: Gpio31::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio32: Gpio32::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio33: Gpio33::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio34: Gpio34::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio35: Gpio35::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio36: Gpio36::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio37: Gpio37::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio38: Gpio38::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio39: Gpio39::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio40: Gpio40::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio41: Gpio41::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio42: Gpio42::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio43: Gpio43::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio44: Gpio44::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio45: Gpio45::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio46: Gpio46::new(), - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] gpio47: Gpio47::new(), - #[cfg(all( - esp32s3, - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(esp32s3)] gpio48: Gpio48::new(), } } @@ -2279,27 +1939,15 @@ mod chip { } #[cfg(esp32c3)] -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] mod chip { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] extern crate alloc; - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] use alloc::boxed::Box; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - use crate::riscv_ulp_hal::sys::*; - - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::interrupt::asynch::HalIsrNotification; use crate::adc::{ADC1, ADC2}; @@ -2311,7 +1959,6 @@ mod chip { pub(crate) static mut PIN_ISR_HANDLER: [Option>; 22] = [PIN_ISR_INIT; 22]; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) static PIN_NOTIF: [HalIsrNotification; 22] = [PIN_NOTIF_INIT; 22]; // NOTE: Gpio12 - Gpio17 are used by SPI0/SPI1 for external PSRAM/SPI Flash and @@ -2399,27 +2046,15 @@ mod chip { } #[cfg(esp32c2)] -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] mod chip { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] extern crate alloc; - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] use alloc::boxed::Box; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - use crate::riscv_ulp_hal::sys::*; - - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::interrupt::asynch::HalIsrNotification; use crate::adc::ADC1; @@ -2431,7 +2066,6 @@ mod chip { pub(crate) static mut PIN_ISR_HANDLER: [Option>; 20] = [PIN_ISR_INIT; 20]; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) static PIN_NOTIF: [HalIsrNotification; 20] = [PIN_NOTIF_INIT; 20]; // NOTE: Gpio12 - Gpio17 are used by SPI0/SPI1 for external PSRAM/SPI Flash and @@ -2516,27 +2150,15 @@ mod chip { } #[cfg(esp32h2)] -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] mod chip { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] extern crate alloc; - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] use alloc::boxed::Box; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - use crate::riscv_ulp_hal::sys::*; - - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::interrupt::asynch::HalIsrNotification; use crate::adc::ADC1; @@ -2548,7 +2170,6 @@ mod chip { pub(crate) static mut PIN_ISR_HANDLER: [Option>; 20] = [PIN_ISR_INIT; 20]; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) static PIN_NOTIF: [HalIsrNotification; 20] = [PIN_NOTIF_INIT; 20]; // NOTE: Gpio12 - Gpio17 are used by SPI0/SPI1 for external PSRAM/SPI Flash and @@ -2636,25 +2257,14 @@ mod chip { #[cfg(any(esp32c5, esp32c6, esp32p4))] // TODO: Implement proper pin layout for esp32c5 and esp32p4 mod chip { - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] extern crate alloc; - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] use alloc::boxed::Box; - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use esp_idf_sys::*; - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] - use crate::riscv_ulp_hal::sys::*; - - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::interrupt::asynch::HalIsrNotification; use crate::adc::ADC1; @@ -2662,15 +2272,11 @@ mod chip { use super::*; #[allow(clippy::type_complexity)] - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - feature = "alloc" - ))] + #[cfg(feature = "alloc")] pub(crate) static mut PIN_ISR_HANDLER: [Option>; 30] = [PIN_ISR_INIT; 30]; #[allow(clippy::type_complexity)] - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub(crate) static PIN_NOTIF: [HalIsrNotification; 30] = [PIN_NOTIF_INIT; 30]; // NOTE: Gpio26 - Gpio32 (and Gpio33 - Gpio37 if using Octal RAM/Flash) are used @@ -2702,15 +2308,10 @@ mod chip { pin!(Gpio23:23, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pin!(Gpio24:24, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pin!(Gpio25:25, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio26:26, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio27:27, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio28:28, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio29:29, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pin!(Gpio30:30, IO, NORTC:0, NOADC:0, NODAC:0, NOTOUCH:0); pub struct Pins { @@ -2740,15 +2341,10 @@ mod chip { pub gpio23: Gpio23, pub gpio24: Gpio24, pub gpio25: Gpio25, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio26: Gpio26, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio27: Gpio27, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio28: Gpio28, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio29: Gpio29, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub gpio30: Gpio30, } @@ -2785,15 +2381,10 @@ mod chip { gpio23: Gpio23::new(), gpio24: Gpio24::new(), gpio25: Gpio25::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio26: Gpio26::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio27: Gpio27::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio28: Gpio28::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio29: Gpio29::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] gpio30: Gpio30::new(), } } diff --git a/src/lib.rs b/src/lib.rs index e20da71ed..81fb47dcc 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -6,108 +6,53 @@ #![cfg_attr(feature = "nightly", feature(doc_cfg))] #![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))] -#[cfg(all(not(feature = "riscv-ulp-hal"), not(feature = "esp-idf-sys")))] -compile_error!("Neither feature `esp-idf-sys`, nor feature `riscv-ulp-hal` is enabled"); - -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(esp_idf_comp_driver_enabled) -))] +#[cfg(not(esp_idf_comp_driver_enabled))] compile_error!("esp-idf-hal requires the `driver` ESP-IDF component to be enabled"); -#[cfg(all( - any( - feature = "std", - feature = "alloc", - feature = "critical-section-interrupt", - feature = "critical-section-mutex" - ), - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")) -))] -compile_error!("Enabling feature `riscv-ulp-hal` implies no other feature is enabled"); - -#[cfg(all( - all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")), - not(esp32s2) -))] -compile_error!("Feature `riscv-ulp-hal` is currently only supported on esp32s2"); - -#[macro_use] -pub mod riscv_ulp_hal; - pub mod adc; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod can; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod cpu; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod delay; pub mod gpio; #[cfg(all(esp32, esp_idf_version_major = "4"))] pub mod hall; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod i2c; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp_idf_comp_driver_enabled -))] #[cfg_attr( feature = "nightly", doc(cfg(all(esp_idf_soc_i2s_supported, esp_idf_comp_driver_enabled))) )] pub mod i2s; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod interrupt; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod io; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod ledc; -#[cfg(all( - any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) -))] +#[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))] pub mod mac; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod modem; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) -))] +#[cfg(any(esp32, esp32s2, esp32s3))] pub mod pcnt; pub mod peripheral; pub mod peripherals; pub mod prelude; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod reset; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod rmt; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod rom; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod spi; pub mod sys; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod task; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod timer; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub mod uart; #[cfg(all( any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) + esp_idf_comp_ulp_enabled ))] pub mod ulp; pub mod units; -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -pub use crate::riscv_ulp_hal::delay; - // This is used to create `embedded_hal` compatible error structs // that preserve original `EspError`. // // Example: // embedded_hal_error!(I2cError, embedded_hal::i2c::Error, embedded_hal::i2c::ErrorKind) -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] #[allow(unused_macros)] macro_rules! embedded_hal_error { ($error:ident, $errortrait:ty, $kind:ty) => { @@ -157,53 +102,6 @@ macro_rules! embedded_hal_error { }; } -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -#[allow(unused_macros)] -macro_rules! embedded_hal_error { - ($error:ident, $errortrait:ty, $kind:ty) => { - #[derive(Debug, Copy, Clone, Eq, PartialEq)] - pub struct $error { - kind: $kind, - cause: crate::riscv_ulp_hal::sys::EspError, - } - - impl $error { - pub fn new(kind: $kind, cause: crate::riscv_ulp_hal::sys::EspError) -> Self { - Self { kind, cause } - } - pub fn other(cause: crate::riscv_ulp_hal::sys::EspError) -> Self { - Self::new(<$kind>::Other, cause) - } - pub fn cause(&self) -> crate::riscv_ulp_hal::sys::EspError { - self.cause - } - } - impl From for $error { - fn from(e: crate::riscv_ulp_hal::sys::EspError) -> Self { - Self::other(e) - } - } - - impl $errortrait for $error { - fn kind(&self) -> $kind { - self.kind - } - } - - impl core::fmt::Display for $error { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!( - f, - "{} {{ kind: {}, cause: {} }}", - stringify!($error), - self.kind, - self.cause() - ) - } - } - }; -} - #[macro_export] #[allow(unused_macros)] macro_rules! into_ref { diff --git a/src/peripherals.rs b/src/peripherals.rs index 512c173d2..0a44dd4f9 100644 --- a/src/peripherals.rs +++ b/src/peripherals.rs @@ -1,208 +1,105 @@ use crate::adc; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::can; use crate::gpio; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::i2c; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp_idf_soc_i2s_supported, - esp_idf_comp_driver_enabled -))] +#[cfg(esp_idf_soc_i2s_supported)] use crate::i2s; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::ledc; -#[cfg(all( - any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) -))] +#[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))] use crate::mac; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::modem; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) -))] +#[cfg(any(esp32, esp32s2, esp32s3))] use crate::pcnt; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::rmt; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::spi; -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any( - all( - not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), - esp_idf_esp_task_wdt_en - ), - any(esp_idf_version_major = "4", esp_idf_version = "5.0") - ) +#[cfg(any( + all( + not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), + esp_idf_esp_task_wdt_en + ), + any(esp_idf_version_major = "4", esp_idf_version = "5.0") ))] use crate::task::watchdog; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::timer; -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] use crate::uart; #[cfg(all( any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), esp_idf_comp_ulp_enabled ))] use crate::ulp; pub struct Peripherals { pub pins: gpio::Pins, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub uart0: uart::UART0, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub uart1: uart::UART1, - #[cfg(all( - any(esp32, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(any(esp32, esp32s3))] pub uart2: uart::UART2, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub i2c0: i2c::I2C0, - #[cfg(all( - not(any(esp32c3, esp32c2, esp32c6)), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32c6)))] pub i2c1: i2c::I2C1, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp_idf_soc_i2s_supported, - esp_idf_comp_driver_enabled - ))] + #[cfg(esp_idf_soc_i2s_supported)] pub i2s0: i2s::I2S0, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp_idf_soc_i2s_supported, - esp_idf_comp_driver_enabled, - any(esp32, esp32s3) - ))] + #[cfg(all(esp_idf_soc_i2s_supported, any(esp32, esp32s3)))] pub i2s1: i2s::I2S1, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub spi1: spi::SPI1, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub spi2: spi::SPI2, - #[cfg(all( - any(esp32, esp32s2, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub spi3: spi::SPI3, pub adc1: adc::ADC1, #[cfg(any(esp32, esp32s2, esp32s3, esp32c3))] pub adc2: adc::ADC2, // TODO: Check the pulse counter story for c2, h2, c5, c6, and p4 - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub pcnt0: pcnt::PCNT0, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub pcnt1: pcnt::PCNT1, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub pcnt2: pcnt::PCNT2, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub pcnt3: pcnt::PCNT3, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pub pcnt4: pcnt::PCNT4, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pub pcnt5: pcnt::PCNT5, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pub pcnt6: pcnt::PCNT6, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pub pcnt7: pcnt::PCNT7, #[cfg(all(esp32, esp_idf_version_major = "4"))] pub hall_sensor: crate::hall::HallSensor, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub can: can::CAN, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub ledc: ledc::LEDC, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub rmt: rmt::RMT, #[cfg(all( any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), esp_idf_comp_ulp_enabled ))] pub ulp: ulp::ULP, - #[cfg(all( - any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))] pub mac: mac::MAC, - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub modem: modem::Modem, // TODO: Check the timer story for c2, h2, c5, c6, and p4 - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer00") - ))] pub timer00: timer::TIMER00, - #[cfg(all( - any(esp32, esp32s2, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer01") - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub timer01: timer::TIMER01, - #[cfg(all( - not(esp32c2), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer10") - ))] + #[cfg(not(esp32c2))] pub timer10: timer::TIMER10, - #[cfg(all( - any(esp32, esp32s2, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer11") - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pub timer11: timer::TIMER11, - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any( - all( - not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), - esp_idf_esp_task_wdt_en - ), - any(esp_idf_version_major = "4", esp_idf_version = "5.0") - ) + #[cfg(any( + all( + not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), + esp_idf_esp_task_wdt_en + ), + any(esp_idf_version_major = "4", esp_idf_version = "5.0") ))] pub twdt: watchdog::TWDT, } -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -static mut TAKEN: bool = false; - -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] static TAKEN: core::sync::atomic::AtomicBool = core::sync::atomic::AtomicBool::new(false); - -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] static TAKEN_CS: crate::task::CriticalSection = crate::task::CriticalSection::new(); impl Peripherals { - #[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] pub fn take() -> Result { if unsafe { TAKEN } { panic!("Peripheral already taken") @@ -214,7 +111,6 @@ impl Peripherals { } } - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub fn take() -> Result { if TAKEN.load(core::sync::atomic::Ordering::SeqCst) { Err(crate::sys::EspError::from_infallible::< @@ -241,140 +137,66 @@ impl Peripherals { pub unsafe fn new() -> Self { Self { pins: gpio::Pins::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] uart0: uart::UART0::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] uart1: uart::UART1::new(), - #[cfg(all( - any(esp32, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(any(esp32, esp32s3))] uart2: uart::UART2::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] i2c0: i2c::I2C0::new(), - #[cfg(all( - not(any(esp32c3, esp32c2, esp32c6)), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(not(any(esp32c3, esp32c2, esp32c6)))] i2c1: i2c::I2C1::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp_idf_soc_i2s_supported, - esp_idf_comp_driver_enabled - ))] + #[cfg(esp_idf_soc_i2s_supported)] i2s0: i2s::I2S0::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp_idf_soc_i2s_supported, - esp_idf_comp_driver_enabled, - any(esp32, esp32s3) - ))] + #[cfg(all(esp_idf_soc_i2s_supported, any(esp32, esp32s3)))] i2s1: i2s::I2S1::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] spi1: spi::SPI1::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] spi2: spi::SPI2::new(), - #[cfg(all( - any(esp32, esp32s2, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] spi3: spi::SPI3::new(), adc1: adc::ADC1::new(), #[cfg(any(esp32, esp32s2, esp32s3, esp32c3))] adc2: adc::ADC2::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pcnt0: pcnt::PCNT0::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pcnt1: pcnt::PCNT1::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pcnt2: pcnt::PCNT2::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any(esp32, esp32s2, esp32s3) - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] pcnt3: pcnt::PCNT3::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pcnt4: pcnt::PCNT4::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pcnt5: pcnt::PCNT5::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pcnt6: pcnt::PCNT6::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - esp32 - ))] + #[cfg(esp32)] pcnt7: pcnt::PCNT7::new(), #[cfg(all(esp32, esp_idf_version_major = "4"))] hall_sensor: crate::hall::HallSensor::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] can: can::CAN::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] ledc: ledc::LEDC::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] rmt: rmt::RMT::new(), #[cfg(all( any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), esp_idf_comp_ulp_enabled ))] ulp: ulp::ULP::new(), - #[cfg(all( - any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) - ))] + #[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))] mac: mac::MAC::new(), - #[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] modem: modem::Modem::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer00") - ))] timer00: timer::TIMER00::new(), - #[cfg(all( - any(esp32, esp32s2, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer01") - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] timer01: timer::TIMER01::new(), - #[cfg(all( - not(esp32c2), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer10") - ))] + #[cfg(not(esp32c2))] timer10: timer::TIMER10::new(), - #[cfg(all( - any(esp32, esp32s2, esp32s3), - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - not(feature = "embassy-time-isr-queue-timer11") - ))] + #[cfg(any(esp32, esp32s2, esp32s3))] timer11: timer::TIMER11::new(), - #[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any( - all( - not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), - esp_idf_esp_task_wdt_en - ), - any(esp_idf_version_major = "4", esp_idf_version = "5.0") - ) + #[cfg(any( + all( + not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), + esp_idf_esp_task_wdt_en + ), + any(esp_idf_version_major = "4", esp_idf_version = "5.0") ))] twdt: watchdog::TWDT::new(), } diff --git a/src/riscv_ulp_hal.rs b/src/riscv_ulp_hal.rs deleted file mode 100644 index 744f10301..000000000 --- a/src/riscv_ulp_hal.rs +++ /dev/null @@ -1,12 +0,0 @@ -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -mod pac; -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -mod reg; - -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -#[macro_use] -pub mod sys; -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -pub mod delay; -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -pub mod start; diff --git a/src/riscv_ulp_hal/delay.rs b/src/riscv_ulp_hal/delay.rs deleted file mode 100644 index 55bc8ee1a..000000000 --- a/src/riscv_ulp_hal/delay.rs +++ /dev/null @@ -1,57 +0,0 @@ -use super::sys::*; - -/// Busy-loop based delay for the RiscV ULP coprocessor -pub struct Ulp; - -impl embedded_hal_0_2::blocking::delay::DelayUs for Ulp { - fn delay_us(&mut self, us: u32) { - delay_cycles(us * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM); - } -} - -impl embedded_hal_0_2::blocking::delay::DelayUs for Ulp { - fn delay_us(&mut self, us: u16) { - delay_cycles(us as u32 * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM); - } -} - -impl embedded_hal_0_2::blocking::delay::DelayUs for Ulp { - fn delay_us(&mut self, us: u8) { - delay_cycles(us as u32 * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM); - } -} - -impl embedded_hal_0_2::blocking::delay::DelayMs for Ulp { - fn delay_ms(&mut self, ms: u32) { - delay_cycles(ms * ULP_RISCV_CYCLES_PER_MS); - } -} - -impl embedded_hal_0_2::blocking::delay::DelayMs for Ulp { - fn delay_ms(&mut self, ms: u16) { - delay_cycles(ms as u32 * ULP_RISCV_CYCLES_PER_MS); - } -} - -impl embedded_hal_0_2::blocking::delay::DelayMs for Ulp { - fn delay_ms(&mut self, ms: u8) { - delay_cycles(ms as u32 * ULP_RISCV_CYCLES_PER_MS); - } -} - -impl embedded_hal::delay::DelayNs for Ulp { - fn delay_ns(&mut self, ns: u32) { - delay_cycles(ns * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM) - } - - fn delay_ms(&mut self, ms: u32) { - delay_cycles(ms * ULP_RISCV_CYCLES_PER_MS) - } -} - -#[inline(always)] -fn delay_cycles(cycles: u32) { - let start = get_ccount(); - - while get_ccount() - start < cycles { /* Wait */ } -} diff --git a/src/riscv_ulp_hal/pac.rs b/src/riscv_ulp_hal/pac.rs deleted file mode 100644 index 1284c4df9..000000000 --- a/src/riscv_ulp_hal/pac.rs +++ /dev/null @@ -1,66 +0,0 @@ -#![allow(dead_code)] - -/// This module is a manual translation of a bunch of C files from current ESP-IDF master (currently ESP32-S2 specific): -/// - https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s2/include/soc/soc.h (a subset) -/// - https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s2/include/soc/sens_reg.h (a subset) -/// - https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s2/include/soc/rtc_io_reg.h (a subset) -use super::reg::bit; - -pub const DR_REG_SENS_BASE: u32 = 0x3f408800; -pub const DR_REG_RTCIO_BASE: u32 = 0x3ff48400; -pub const DR_REG_RTCCNTL_BASE: u32 = 0x3f408000; - -pub const RTC_CNTL_COCPU_CTRL_REG: u32 = DR_REG_RTCCNTL_BASE + 0x0100; -pub const RTC_CNTL_COCPU_DONE: u32 = bit(25); -pub const RTC_CNTL_COCPU_SHUT_RESET_EN: u32 = bit(22); -pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS: u32 = 0x000000FF; -pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V: u32 = 0xFF; -pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S: u32 = 14; - -pub const RTC_CNTL_STATE0_REG: u32 = DR_REG_RTCCNTL_BASE + 0x0018; -pub const RTC_CNTL_SW_CPU_INT: u32 = bit(0); -pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN: u32 = bit(31); -pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN_V: u32 = 0x1; -pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN_S: u32 = 31; - -pub const SENS_SAR_IO_MUX_CONF_REG: u32 = DR_REG_SENS_BASE + 0x0144; -pub const SENS_IOMUX_CLK_GATE_EN_M: u32 = bit(31); - -pub const RTC_IO_TOUCH_PAD0_REG: u32 = DR_REG_RTCIO_BASE + 0x84; -pub const RTC_IO_TOUCH_PAD0_DRV: u32 = 0x00000003; -pub const RTC_IO_TOUCH_PAD0_DRV_V: u32 = 0x3; -pub const RTC_IO_TOUCH_PAD0_DRV_S: u32 = 29; -pub const RTC_IO_TOUCH_PAD0_MUX_SEL: u32 = bit(19); -pub const RTC_IO_TOUCH_PAD0_FUN_SEL: u32 = 0x00000003; -pub const RTC_IO_TOUCH_PAD0_FUN_SEL_V: u32 = 0x3; -pub const RTC_IO_TOUCH_PAD0_FUN_SEL_S: u32 = 17; -pub const RTC_IO_TOUCH_PAD0_FUN_IE: u32 = bit(13); -pub const RTC_IO_TOUCH_PAD0_FUN_IE_V: u32 = 0x01; -pub const RTC_IO_TOUCH_PAD0_FUN_IE_S: u32 = 13; -pub const RTC_IO_TOUCH_PAD0_RUE: u32 = bit(27); -pub const RTC_IO_TOUCH_PAD0_RDE: u32 = bit(28); - -pub const RTC_GPIO_ENABLE_W1TS_REG: u32 = DR_REG_RTCIO_BASE + 0x10; -pub const RTC_GPIO_ENABLE_W1TS: u32 = 0x0003FFFF; -pub const RTC_GPIO_ENABLE_W1TS_V: u32 = 0x3FFFF; -pub const RTC_GPIO_ENABLE_W1TS_S: u32 = 10; - -pub const RTC_GPIO_ENABLE_W1TC_REG: u32 = DR_REG_RTCIO_BASE + 0x14; -pub const RTC_GPIO_ENABLE_W1TC: u32 = 0x0003FFFF; -pub const RTC_GPIO_ENABLE_W1TC_V: u32 = 0x3FFFF; -pub const RTC_GPIO_ENABLE_W1TC_S: u32 = 10; - -pub const RTC_GPIO_IN_REG: u32 = DR_REG_RTCIO_BASE + 0x24; -pub const RTC_GPIO_IN_NEXT: u32 = 0x0003FFFF; -pub const RTC_GPIO_IN_NEXT_V: u32 = 0x3FFFF; -pub const RTC_GPIO_IN_NEXT_S: u32 = 10; - -pub const RTC_GPIO_OUT_W1TS_REG: u32 = DR_REG_RTCIO_BASE + 0x4; -pub const RTC_GPIO_OUT_DATA_W1TS: u32 = 0x0003FFFF; -pub const RTC_GPIO_OUT_DATA_W1TS_V: u32 = 0x3FFFF; -pub const RTC_GPIO_OUT_DATA_W1TS_S: u32 = 10; - -pub const RTC_GPIO_OUT_W1TC_REG: u32 = DR_REG_RTCIO_BASE + 0x8; -pub const RTC_GPIO_OUT_DATA_W1TC: u32 = 0x0003FFFF; -pub const RTC_GPIO_OUT_DATA_W1TC_V: u32 = 0x3FFFF; -pub const RTC_GPIO_OUT_DATA_W1TC_S: u32 = 10; diff --git a/src/riscv_ulp_hal/reg.rs b/src/riscv_ulp_hal/reg.rs deleted file mode 100644 index b37efffdb..000000000 --- a/src/riscv_ulp_hal/reg.rs +++ /dev/null @@ -1,173 +0,0 @@ -#![allow(dead_code)] - -/// This module is a manual translation of the following C file from current ESP-IDF master: -/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/include/ulp_riscv/ulp_riscv_register_ops.h -use core::ptr::{read_volatile, write_volatile}; - -/* - * When COCPU accesses the RTC register, it needs to convert the access address. - * When COCPU accesses the RTC memory, dont need to convert the access address. - */ -#[inline(always)] -pub unsafe fn write_rtc_mem(addr: u32, val: i32) { - write_volatile(addr as *mut i32, val); -} - -#[inline(always)] -pub unsafe fn read_rtc_mem(addr: u32) -> i32 { - read_volatile(addr as *const i32) -} - -/* - * When COCPU accesses the RTC register, it needs to convert the access address. - * When COCPU accesses the RTC memory, dont need to convert the access address. - */ -#[inline(always)] -pub const fn riscv_reg_conv(addr: u32) -> u32 { - ((addr & 0xffff) << 3) & 0xe000 | addr & 0x1fff | 0x8000 -} - -#[inline(always)] -pub const fn ets_uncached_addr(addr: u32) -> u32 { - riscv_reg_conv(addr) -} - -#[inline(always)] -pub const fn bit(nr: u32) -> u32 { - 1u32 << nr -} - -// Write value to register -#[inline(always)] -pub unsafe fn reg_write(r: u32, v: u32) { - write_volatile(riscv_reg_conv(r) as *mut u32, v); -} - -// Read value from register -#[inline(always)] -pub unsafe fn reg_read(r: u32) -> u32 { - read_volatile(riscv_reg_conv(r) as *const u32) -} - -// Get bit or get bits from register -#[inline(always)] -pub unsafe fn reg_get_bit(r: u32, b: u32) -> u32 { - read_volatile(riscv_reg_conv(r) as *const u32) & b -} - -// Get bit or get bits from register -#[inline(always)] -pub unsafe fn reg_set_bit(r: u32, b: u32) { - let addr = riscv_reg_conv(r) as *mut u32; - write_volatile(addr, read_volatile(addr) | b); -} - -// Clear bit or clear bits of register -#[inline(always)] -pub unsafe fn reg_clr_bit(r: u32, b: u32) { - let addr = riscv_reg_conv(r) as *mut u32; - write_volatile(addr, read_volatile(addr) & !b); -} - -// Set bits of register controlled by mask -#[inline(always)] -pub unsafe fn reg_set_bits(r: u32, b: u32, m: u32) { - let addr = riscv_reg_conv(r) as *mut u32; - write_volatile(addr, read_volatile(addr) & !m | b & m); -} - -// Get field from register, uses field _S & _V to determine mask -#[inline(always)] -pub unsafe fn reg_get_field(r: u32, f_s: u32, f_v: u32) -> u32 { - (reg_read(r) >> f_s) & f_v -} - -// Set field of a register from variable, uses field _S & _V to determine mask -#[inline(always)] -pub unsafe fn reg_set_field(r: u32, f_s: u32, f_v: u32, v: u32) { - reg_write(r, (reg_read(r) & !(f_v << f_s)) | ((v & f_v) << f_s)); -} - -// Get field value from a variable, used when _f is not left shifted by _f##_S -#[inline(always)] -pub const fn value_get_field(r: u32, f: u32, f_s: u32) -> u32 { - (r >> f_s) & f -} - -// Get field value from a variable, used when _f is left shifted by _f##_S -#[inline(always)] -pub const fn value_get_field2(r: u32, f: u32, f_s: u32) -> u32 { - (r & f) >> f_s -} - -// Set field value to a variable, used when _f is not left shifted by _f##_S -#[inline(always)] -pub const fn value_set_field(r: u32, f: u32, f_s: u32, v: u32) -> u32 { - r & !(f << f_s) | (v << f_s) -} - -// Set field value to a variable, used when _f is left shifted by _f##_S -#[inline(always)] -pub const fn value_set_field2(r: u32, f: u32, f_s: u32, v: u32) -> u32 { - r & !f | (v << f_s) -} - -// Generate a value from a field value, used when _f is not left shifted by _f##_S -#[inline(always)] -pub const fn field_to_value(f: u32, f_s: u32, v: u32) -> u32 { - (v & f) << f_s -} - -// Generate a value from a field value, used when _f is left shifted by _f##_S -#[inline(always)] -pub const fn field_to_value2(f: u32, f_s: u32, v: u32) -> u32 { - (v << f_s) & f -} - -// Read value from register -#[inline(always)] -pub unsafe fn read_peri_reg(addr: u32) -> u32 { - read_volatile(ets_uncached_addr(addr) as *const u32) -} - -// Write value to register -#[inline(always)] -pub unsafe fn write_peri_reg(addr: u32, v: u32) { - write_volatile(ets_uncached_addr(addr) as *mut u32, v); -} - -// Clear bits of register controlled by mask -#[inline(always)] -pub unsafe fn clear_peri_reg_mask(addr: u32, mask: u32) { - write_peri_reg(addr, read_peri_reg(addr) & !mask); -} - -#[inline(always)] -pub unsafe fn set_peri_reg_mask(addr: u32, mask: u32) { - write_peri_reg(addr, read_peri_reg(addr) | mask); -} - -// Get bits of register controlled by mask -#[inline(always)] -pub unsafe fn get_peri_reg_mask(addr: u32, mask: u32) -> u32 { - read_peri_reg(addr) & mask -} - -// Get bits of register controlled by highest bit and lowest bit -#[inline(always)] -pub unsafe fn get_peri_reg_bits(addr: u32, bit_map: u32, shift: u8) -> u32 { - (read_peri_reg(addr) & (bit_map << shift)) >> shift -} - -// Set bits of register controlled by mask and shift -pub unsafe fn set_peri_reg_bits(addr: u32, bit_map: u32, value: u32, shift: u8) { - write_peri_reg( - addr, - read_peri_reg(addr) & !(bit_map << shift) | ((value & bit_map) << shift), - ); -} - -// Get field of register -pub unsafe fn get_peri_reg_bits2(addr: u32, mask: u32, shift: u8) -> u32 { - (read_peri_reg(addr) >> shift) & mask -} diff --git a/src/riscv_ulp_hal/start.rs b/src/riscv_ulp_hal/start.rs deleted file mode 100644 index d8a6d668b..000000000 --- a/src/riscv_ulp_hal/start.rs +++ /dev/null @@ -1,179 +0,0 @@ -//! Minimal startup / runtime for ESP32-SXX RISC-V ULPs -//! Adapted from riscv-rt/src/lib.rs - -#![deny(missing_docs)] - -use super::sys::cpu; - -#[export_name = "error: ulp_start appears more than once in the dependency graph"] -#[doc(hidden)] -pub static __ONCE__: () = (); - -/// # Safety -/// -/// Rust entry point (_start_rust) -/// This function is NOT supposed to be called from use code -/// -/// Calls main. This function never returns. -#[link_section = ".start.rust"] -#[export_name = "_start_rust"] -pub unsafe extern "C" fn start_rust() -> ! { - #[rustfmt::skip] - extern "Rust" { - // This symbol will be provided by the user - fn main(); - } - - cpu::rescue_from_monitor(); - - main(); - - cpu::shutdown(); -} - -/// Registers saved in trap handler -#[allow(missing_docs)] -#[repr(C)] -pub struct TrapFrame { - pub ra: usize, - pub t0: usize, - pub t1: usize, - pub t2: usize, - pub t3: usize, - pub t4: usize, - pub t5: usize, - pub t6: usize, - pub a0: usize, - pub a1: usize, - pub a2: usize, - pub a3: usize, - pub a4: usize, - pub a5: usize, - pub a6: usize, - pub a7: usize, -} - -/// # Safety -/// -/// Trap entry point rust (_start_trap_rust) -/// This function is NOT supposed to be called from use code -/// -/// `mcause` is read to determine the cause of the trap. XLEN-1 bit indicates -/// if it's an interrupt or an exception. The result is examined and ExceptionHandler -/// or one of the core interrupt handlers is called. -#[link_section = ".trap.rust"] -#[export_name = "_start_trap_rust"] -pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { - // use riscv::register::mcause; - - extern "C" { - fn ExceptionHandler(trap_frame: &TrapFrame); - #[allow(dead_code)] - fn DefaultHandler(); - } - - // let cause = mcause::read(); - // if cause.is_exception() { - ExceptionHandler(trap_frame.as_ref().unwrap()) - // } else { - // let code = cause.code(); - // if code < __INTERRUPTS.len() { - // let h = &__INTERRUPTS[code]; - // if h.reserved == 0 { - // DefaultHandler(); - // } else { - // (h.handler)(); - // } - // } else { - // DefaultHandler(); - // } - // } -} - -#[doc(hidden)] -#[no_mangle] -#[allow(unused_variables, non_snake_case)] -pub fn DefaultExceptionHandler(trap_frame: &TrapFrame) -> ! { - loop { - // Prevent this from turning into a UDF instruction - // see rust-lang/rust#28728 for details - continue; - } -} - -#[doc(hidden)] -#[no_mangle] -#[allow(unused_variables, non_snake_case)] -pub fn DefaultInterruptHandler() { - loop { - // Prevent this from turning into a UDF instruction - // see rust-lang/rust#28728 for details - continue; - } -} - -/* Interrupts */ -#[doc(hidden)] -pub enum Interrupt { - UserSoft, - SupervisorSoft, - MachineSoft, - UserTimer, - SupervisorTimer, - MachineTimer, - UserExternal, - SupervisorExternal, - MachineExternal, -} - -pub use self::Interrupt as interrupt; - -extern "C" { - fn UserSoft(); - fn SupervisorSoft(); - fn MachineSoft(); - fn UserTimer(); - fn SupervisorTimer(); - fn MachineTimer(); - fn UserExternal(); - fn SupervisorExternal(); - fn MachineExternal(); -} - -#[doc(hidden)] -pub union Vector { - handler: unsafe extern "C" fn(), - reserved: usize, -} - -#[doc(hidden)] -#[allow(dead_code)] -#[no_mangle] -pub static __INTERRUPTS: [Vector; 12] = [ - Vector { handler: UserSoft }, - Vector { - handler: SupervisorSoft, - }, - Vector { reserved: 0 }, - Vector { - handler: MachineSoft, - }, - Vector { handler: UserTimer }, - Vector { - handler: SupervisorTimer, - }, - Vector { reserved: 0 }, - Vector { - handler: MachineTimer, - }, - Vector { - handler: UserExternal, - }, - Vector { - handler: SupervisorExternal, - }, - Vector { reserved: 0 }, - Vector { - handler: MachineExternal, - }, -]; diff --git a/src/riscv_ulp_hal/sys.rs b/src/riscv_ulp_hal/sys.rs deleted file mode 100644 index 20536c5c8..000000000 --- a/src/riscv_ulp_hal/sys.rs +++ /dev/null @@ -1,28 +0,0 @@ -/// A mini "esp-idf-ulp-sys" module exposing stuff on top of which the ULP HAL support is implemented -/// (currently, only GPIO) + some utilities for the riscv ULP processor -pub use self::cpu::*; -pub use self::gpio::*; - -pub mod cpu; -#[allow(clippy::missing_safety_doc)] -pub mod gpio; - -pub type EspError = core::convert::Infallible; - -#[macro_export] -macro_rules! esp_result { - ($err:expr, $value:expr) => {{ - $err; - - Ok($value) - }}; -} - -#[macro_export] -macro_rules! esp { - ($err:expr) => {{ - $err; - - core::result::Result::<(), EspError>::Ok(()) - }}; -} diff --git a/src/riscv_ulp_hal/sys/cpu.rs b/src/riscv_ulp_hal/sys/cpu.rs deleted file mode 100644 index f758f4252..000000000 --- a/src/riscv_ulp_hal/sys/cpu.rs +++ /dev/null @@ -1,71 +0,0 @@ -#![allow(dead_code)] - -/// This module is a manual translation of the following C file from current ESP-IDF master: -/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/include/ulp_riscv/ulp_utils.h -/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/ulp_utils.c -use core::arch::asm; - -use crate::riscv_ulp_hal::pac::*; -use crate::riscv_ulp_hal::reg::*; - -pub const ULP_RISCV_CYCLES_PER_US_NUM: u32 = 85; -pub const ULP_RISCV_CYCLES_PER_US_DENUM: u32 = 10; -pub const ULP_RISCV_CYCLES_PER_MS: u32 = - ULP_RISCV_CYCLES_PER_US_NUM * (1000 / ULP_RISCV_CYCLES_PER_US_DENUM); - -#[inline(always)] -pub fn get_ccount() -> u32 { - #[allow(unused_assignments)] - let mut ccount = 0; - - unsafe { - asm!("rdcycle {}", out(reg) ccount); - } - - ccount -} - -pub fn wakeup_main_processor() { - unsafe { set_peri_reg_mask(RTC_CNTL_STATE0_REG, RTC_CNTL_SW_CPU_INT) }; -} - -pub fn rescue_from_monitor() { - // Rescue RISCV from monitor state - unsafe { - clear_peri_reg_mask( - RTC_CNTL_COCPU_CTRL_REG, - RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN, - ) - }; -} - -pub fn enable_timer(enable: bool) { - unsafe { - if enable { - set_peri_reg_mask(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); - } else { - clear_peri_reg_mask(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); - } - } -} - -pub fn shutdown() -> ! { - unsafe { - // Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. - reg_set_field( - RTC_CNTL_COCPU_CTRL_REG, - RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S, - RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V, - 0x3F, - ); - - // Suspends the ulp operation - set_peri_reg_mask(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE); - - // Resets the processor - set_peri_reg_mask(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - } - - #[allow(clippy::empty_loop)] - loop {} -} diff --git a/src/riscv_ulp_hal/sys/gpio.rs b/src/riscv_ulp_hal/sys/gpio.rs deleted file mode 100644 index 64e516f80..000000000 --- a/src/riscv_ulp_hal/sys/gpio.rs +++ /dev/null @@ -1,204 +0,0 @@ -/// A mini "esp-idf-ulp-sys" module exposing stuff on top of which the ULP HAL support is implemented -/// (currently, only GPIO) -/// Implemented as a manual transation of a few C fields from current ESP-IDF S2 master: -/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/include/ulp_riscv/ulp_riscv_gpio.h -use crate::riscv_ulp_hal::pac::*; -use crate::riscv_ulp_hal::reg::*; - -#[allow(non_camel_case_types)] -pub type adc_unit_t = i32; -#[allow(non_camel_case_types)] -pub type adc_channel_t = i32; -#[allow(non_camel_case_types)] -pub type dac_channel_t = i32; -#[allow(non_camel_case_types)] -pub type touch_pad_t = i32; -#[allow(non_camel_case_types)] -pub type adc_atten_t = i32; -#[allow(non_camel_case_types)] -pub type gpio_mode_t = u8; -#[allow(non_camel_case_types)] -pub type gpio_pull_mode_t = u8; - -#[allow(non_upper_case_globals)] -pub const adc_unit_t_ADC_UNIT_1: adc_unit_t = 0; -#[allow(non_upper_case_globals)] -pub const adc_unit_t_ADC_UNIT_2: adc_unit_t = 1; - -#[allow(non_upper_case_globals)] -pub const adc_atten_t_ADC_ATTEN_DB_0: adc_atten_t = 0; -#[allow(non_upper_case_globals)] -pub const adc_atten_t_ADC_ATTEN_DB_2_5: adc_atten_t = 1; -#[allow(non_upper_case_globals)] -pub const adc_atten_t_ADC_ATTEN_DB_6: adc_atten_t = 2; -#[allow(non_upper_case_globals)] -pub const adc_atten_t_ADC_ATTEN_DB_11: adc_atten_t = 3; - -#[allow(non_upper_case_globals)] -pub const gpio_mode_t_GPIO_MODE_DISABLE: u8 = 0; -#[allow(non_upper_case_globals)] -pub const gpio_mode_t_GPIO_MODE_INPUT: u8 = 1; -#[allow(non_upper_case_globals)] -pub const gpio_mode_t_GPIO_MODE_OUTPUT: u8 = 2; -#[allow(non_upper_case_globals)] -pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT: u8 = 3; -#[allow(non_upper_case_globals)] -pub const gpio_mode_t_GPIO_MODE_OUTPUT_OD: u8 = 4; -#[allow(non_upper_case_globals)] -pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD: u8 = 5; - -#[allow(non_upper_case_globals)] -pub const gpio_pull_mode_t_GPIO_PULLUP_ONLY: u8 = 0; -#[allow(non_upper_case_globals)] -pub const gpio_pull_mode_t_GPIO_PULLDOWN_ONLY: u8 = 1; -#[allow(non_upper_case_globals)] -pub const gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN: u8 = 2; -#[allow(non_upper_case_globals)] -pub const gpio_pull_mode_t_GPIO_FLOATING: u8 = 3; - -#[inline(always)] -pub unsafe fn gpio_set_direction(gpio_num: i32, direction: u8) { - if direction == gpio_mode_t_GPIO_MODE_DISABLE { - // Deinit - clear_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_MUX_SEL, - ); - return; - } else { - // Init - set_peri_reg_mask(SENS_SAR_IO_MUX_CONF_REG, SENS_IOMUX_CLK_GATE_EN_M); - set_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_MUX_SEL, - ); - reg_set_field( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_FUN_SEL_S, - RTC_IO_TOUCH_PAD0_FUN_SEL_V, - 0, - ); - } - - let input = direction == gpio_mode_t_GPIO_MODE_INPUT - || direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT - || direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD; - let output = direction == gpio_mode_t_GPIO_MODE_OUTPUT - || direction == gpio_mode_t_GPIO_MODE_OUTPUT_OD - || direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT - || direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD; - let od = direction == gpio_mode_t_GPIO_MODE_OUTPUT_OD - || direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD; - - if input { - set_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_FUN_IE, - ); - } else { - clear_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_FUN_IE, - ); - } - - if output { - reg_set_field( - RTC_GPIO_ENABLE_W1TS_REG, - RTC_GPIO_ENABLE_W1TS_S, - RTC_GPIO_ENABLE_W1TS_V, - bit(gpio_num as u32), - ); - reg_set_field( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_DRV_S, - RTC_IO_TOUCH_PAD0_DRV_V, - if od { 1 } else { 0 }, - ); - } else { - reg_set_field( - RTC_GPIO_ENABLE_W1TC_REG, - RTC_GPIO_ENABLE_W1TC_S, - RTC_GPIO_ENABLE_W1TC_V, - bit(gpio_num as u32), - ); - } -} - -#[inline(always)] -pub unsafe fn gpio_set_pull_mode(gpio_num: i32, mode: u8) { - let pullup = - mode == gpio_pull_mode_t_GPIO_PULLUP_ONLY || mode == gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN; - let pulldown = mode == gpio_pull_mode_t_GPIO_PULLDOWN_ONLY - || mode == gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN; - - if pullup { - set_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_RUE, - ); - } else { - clear_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_RUE, - ); - } - - if pulldown { - set_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_RDE, - ); - } else { - clear_peri_reg_mask( - RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4, - RTC_IO_TOUCH_PAD0_RDE, - ); - } -} - -#[inline(always)] -pub unsafe fn gpio_get_level(gpio_num: i32) -> u8 { - if (reg_get_field(RTC_GPIO_IN_REG, RTC_GPIO_IN_NEXT_S, RTC_GPIO_IN_NEXT_V) - & bit(gpio_num as u32)) - != 0 - { - 1 - } else { - 0 - } -} - -#[inline(always)] -pub unsafe fn gpio_set_level(gpio_num: i32, level: u8) { - if level != 0 { - reg_set_field( - RTC_GPIO_OUT_W1TS_REG, - RTC_GPIO_OUT_DATA_W1TS_S, - RTC_GPIO_OUT_DATA_W1TS_V, - bit(gpio_num as u32), - ); - } else { - reg_set_field( - RTC_GPIO_OUT_W1TC_REG, - RTC_GPIO_OUT_DATA_W1TC_S, - RTC_GPIO_OUT_DATA_W1TC_V, - bit(gpio_num as u32), - ); - } -} - -#[inline(always)] -pub unsafe fn gpio_get_output_level(gpio_num: i32) -> u8 { - if (reg_get_field( - RTC_GPIO_OUT_W1TS_REG, - RTC_GPIO_OUT_DATA_W1TS_S, - RTC_GPIO_OUT_DATA_W1TS_V, - ) & bit(gpio_num as u32)) - != 0 - { - 1 - } else { - 0 - } -} diff --git a/src/sys.rs b/src/sys.rs index 0ae833bf5..bc4cb823d 100644 --- a/src/sys.rs +++ b/src/sys.rs @@ -1,5 +1 @@ -#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))] pub use esp_idf_sys::*; - -#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))] -pub use crate::riscv_ulp_hal::sys::*; diff --git a/src/task.rs b/src/task.rs index 77c013ded..19adc7cf5 100644 --- a/src/task.rs +++ b/src/task.rs @@ -487,15 +487,12 @@ impl<'a> Drop for CriticalSectionGuard<'a> { } } -#[cfg(all( - not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), - any( - all( - not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), - esp_idf_esp_task_wdt_en - ), - any(esp_idf_version_major = "4", esp_idf_version = "5.0") - ) +#[cfg(any( + all( + not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), + esp_idf_esp_task_wdt_en + ), + any(esp_idf_version_major = "4", esp_idf_version = "5.0") ))] pub mod watchdog { //! ## Example