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https://github.com/esp-rs/esp-idf-hal.git
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* ULP peripheral; ULP HAL code renamed * Use an enum for the chip cores * riscv-ulp-hal feature bugfixes * Fix the CI for ULP as well
118 lines
2.1 KiB
ArmAsm
118 lines
2.1 KiB
ArmAsm
// NOTE: Adapted from riscv-rt/asm.S
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#define REGBYTES (1 << 2)
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.section .init, "ax"
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.global reset_vector
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.global irq_vector
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// The reset vector, jumps to startup code
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reset_vector:
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j _start
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// Interrupt handler
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.option push
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.option norelax // To prevent an unsupported R_RISCV_ALIGN relocation from being generated
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.balign 16
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irq_vector:
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addi sp, sp, -16*REGBYTES
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sw ra, 0*REGBYTES(sp)
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sw t0, 1*REGBYTES(sp)
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sw t1, 2*REGBYTES(sp)
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sw t2, 3*REGBYTES(sp)
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sw t3, 4*REGBYTES(sp)
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sw t4, 5*REGBYTES(sp)
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sw t5, 6*REGBYTES(sp)
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sw t6, 7*REGBYTES(sp)
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sw a0, 8*REGBYTES(sp)
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sw a1, 9*REGBYTES(sp)
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sw a2, 10*REGBYTES(sp)
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sw a3, 11*REGBYTES(sp)
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sw a4, 12*REGBYTES(sp)
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sw a5, 13*REGBYTES(sp)
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sw a6, 14*REGBYTES(sp)
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sw a7, 15*REGBYTES(sp)
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add a0, sp, zero
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jal ra, _start_trap_rust
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lw ra, 0*REGBYTES(sp)
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lw t0, 1*REGBYTES(sp)
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lw t1, 2*REGBYTES(sp)
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lw t2, 3*REGBYTES(sp)
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lw t3, 4*REGBYTES(sp)
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lw t4, 5*REGBYTES(sp)
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lw t5, 6*REGBYTES(sp)
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lw t6, 7*REGBYTES(sp)
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lw a0, 8*REGBYTES(sp)
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lw a1, 9*REGBYTES(sp)
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lw a2, 10*REGBYTES(sp)
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lw a3, 11*REGBYTES(sp)
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lw a4, 12*REGBYTES(sp)
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lw a5, 13*REGBYTES(sp)
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lw a6, 14*REGBYTES(sp)
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lw a7, 15*REGBYTES(sp)
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addi sp, sp, 16*REGBYTES
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ret
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.option pop
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_start:
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.cfi_startproc
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.cfi_undefined ra
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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.option push
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.option norelax // To prevent an unsupported R_RISCV_ALIGN relocation from being generated
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la gp, __global_pointer$
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.option pop
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// Allocate stack
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la sp, _stack_top
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// Set frame pointer
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add s0, sp, zero
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jal zero, _start_rust
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.cfi_endproc
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loop:
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j loop
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// Make sure there is an abort when linking
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.globl abort
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abort:
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j abort
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