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0afb9e732c
Former-commit-id: bdede6ed1b6f578f2ef046c338caf02d0b29d453 [formerly 7187de361b53e9c8ec121df379b762f2db736ea2] Former-commit-id: 447d58460fbbfd05ffe08428a1288e392637561d
12 lines
274 B
Verilog
12 lines
274 B
Verilog
always @(negedge reset or posedge clk) begin
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if (reset == 0) begin
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d_out <= 16'h0000;
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d_out_mem[resetcount] <= d_out;
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laststoredvalue <= d_out;
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end else begin
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d_out <= d_out + 1'b1;
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end
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end
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always @(bufreadaddr)
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bufreadval = d_out_mem[bufreadaddr]; |