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fix documentation

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This commit is contained in:
Tyler Holmes 2022-01-15 14:39:36 -08:00
parent 63c0370d69
commit a469645439
2 changed files with 12 additions and 6 deletions
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9
src/mpmc.rs
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@ -1,6 +1,7 @@
//! A fixed capacity Multiple-Producer Multiple-Consumer (MPMC) lock-free queue //! A fixed capacity Multiple-Producer Multiple-Consumer (MPMC) lock-free queue
//! //!
//! NOTE: This module is not available on targets that do *not* support CAS operations, e.g. ARMv6-M //! NOTE: This module is not available on targets that do *not* support CAS operations and are not
//! emulated by the [`atomic_polyfill`] crate (e.g., MSP430).
//! //!
//! # Example //! # Example
//! //!
@ -73,8 +74,10 @@
//! //!
//! # Portability //! # Portability
//! //!
//! This module is not exposed to architectures that lack the instructions to implement CAS loops. //! This module requires CAS atomic instructions which are not available on all architectures
//! Those architectures include ARMv6-M (`thumbv6m-none-eabi`) and MSP430 (`msp430-none-elf`). //! (e.g. ARMv6-M (`thumbv6m-none-eabi`) and MSP430 (`msp430-none-elf`)). These atomics can be emulated
//! however with [`atomic_polyfill`], which is enabled with the `cas` feature and is enabled by default
//! for `thumbv6m-none-eabi` and `riscv32` targets. MSP430 is currently not supported by [`atomic_polyfill`].
//! //!
//! # References //! # References
//! //!

9
src/pool/mod.rs
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@ -1,6 +1,7 @@
//! A heap-less, interrupt-safe, lock-free memory pool (\*) //! A heap-less, interrupt-safe, lock-free memory pool (\*)
//! //!
//! NOTE: This module is not available on targets that do *not* support CAS operations, e.g. ARMv6-M //! NOTE: This module is not available on targets that do *not* support CAS operations and are not
//! emulated by the [`atomic_polyfill`] crate (e.g., MSP430).
//! //!
//! (\*) Currently, the implementation is only lock-free *and* `Sync` on ARMv6, ARMv7-{A,R,M} & ARMv8-M //! (\*) Currently, the implementation is only lock-free *and* `Sync` on ARMv6, ARMv7-{A,R,M} & ARMv8-M
//! devices //! devices
@ -59,8 +60,10 @@
//! on the target architecture (see section on ['Soundness'](#soundness) for more information). For //! on the target architecture (see section on ['Soundness'](#soundness) for more information). For
//! this reason, `Pool` only implements `Sync` when compiling for some ARM cores. //! this reason, `Pool` only implements `Sync` when compiling for some ARM cores.
//! //!
//! Also note that ARMv6-M architecture lacks the primitives for CAS loops so this module does *not* //! This module requires CAS atomic instructions which are not available on all architectures
//! exist for `thumbv6m-none-eabi`. //! (e.g. ARMv6-M (`thumbv6m-none-eabi`) and MSP430 (`msp430-none-elf`)). These atomics can be emulated
//! however with [`atomic_polyfill`], which is enabled with the `cas` feature and is enabled by default
//! for `thumbv6m-none-eabi` and `riscv32` targets. MSP430 is currently not supported by [`atomic_polyfill`].
//! //!
//! # Soundness //! # Soundness
//! //!