143: Implement core::fmt::Write for heapless::Vec<u8, N> r=korken89 a=ijl
I didn't see a mention of this in issues or previous pull requests, but I expect it's in scope?
Co-authored-by: ijl <ijl@mailbox.org>
Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
155: Extend ARMv7-R `Pool` support to the bare-metal `armebv7r-` targets r=japaric a=rjsberry
Extends support for singleton `Pool`s to include the `armebv7r-none-eabi` and `armebv7r-none-eabihf` targets.
Co-authored-by: Richard Berry <rjsberry@pm.me>
156: Add optional ufmt impls r=japaric a=dbrgn
By enabling the `ufmt-impl` feature, `uWrite` impls are provided for `String<N>` and `Vec<u8, N>`.
Co-authored-by: Danilo Bargen <mail@dbrgn.ch>
152: Implement Vec::starts_with and Vec::ends_with r=korken89 a=dbrgn
Implementation mostly copied from `std`.
The logic should be covered by documentation tests, so no separate unit tests were added.
Co-authored-by: Danilo Bargen <mail@dbrgn.ch>
136: add the HistoryBuffer type r=korken89 a=birkenfeld
Closes#112
Unfortunately `const` construction won't work since the `Default` or `Clone` bound on `T` can't be used then, so I've not added an internal type to `i.rs`.
Let me know if you think any other traits should be implemented...
Co-authored-by: Georg Brandl <georg@python.org>
147: Implement StableDeref for singleton::Box r=korken89 a=thalesfragoso
There was a discussion in the riot channel about what it's needed for a buffer to be DMA safe, where ra_kete came up with this POC:
https://play.rust-lang.org/?version=stable&mode=debug&edition=2018&gist=339a9a29fb59c080b42b6d77a902acb6
Where it seems that the requirements described in the [Embedonomicon](https://docs.rust-embedded.org/embedonomicon/dma.html#static-bound) doesn't seem to be enough to prevent stack corruption.
If that is really the case and we decide to use `StableDeref` instead, then a implementation for Box is very important to be able to easily use it on DMA APIs and a new point release would be necessary.
CC @korken89
Co-authored-by: thalesfragoso <thales.fragosoz@gmail.com>
142: Extend the ARMv7-A `Pool` support to the bare-metal `armv7a-` targets. r=japaric a=japaric
The built-in rustc targets ended with names that start with `armv7a-` so #140
does not cover them though the intention was to support them; this commit fixes
that
Co-authored-by: Jorge Aparicio <jorge.aparicio@ferrous-systems.com>
The built-in rustc targets ended with names that start with `armv7a-` so #140
does not cover them though the intention was to support them; this commit fixes
that
120: Allow for manual opt-out of CAS features r=japaric a=jamesmunns
I've been working on a bare metal platform lately that does not have CAS (specifically ARMv4 bare metal), and this is not caught by the CPU detection logic in the build.rs. This PR adds a flag that allows for manual specification to avoid CAS features.
Co-authored-by: James Munns <james.munns@ferrous-systems.com>
126: Add DoubleEndedIterator to queue iterators r=japaric a=david-sawatzke
The implementation is pretty straightforward and it's useful
Co-authored-by: David Sawatzke <david-sawatzke@users.noreply.github.com>
Co-authored-by: Jorge Aparicio <jorge@japaric.io>
