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RISC-V: riscv_hwprobe-based feature detection on Linux / Android
This commit implements `riscv_hwprobe`-based feature detection as available on newer versions of the Linux kernel. It also queries whether the vector extensions are enabled using `prctl` but this is not supported on QEMU's userland emulator (as of version 9.2.3) and use the auxiliary vector as a fallback. Currently, all extensions discoverable from the Linux kernel version 6.14 and related extension groups (except "Supm", which reports the existence of `prctl`-based pointer masking control and too OS-dependent) are implemented. Co-Authored-By: Taiki Endo <te316e89@gmail.com>
This commit is contained in:
Tsukasa OI
Amanieu d'Antras
parent
db188b33b3
commit
d5baf4da91
@ -56,11 +56,14 @@ crate from working on applications in which `std` is not available.
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[`cupid`](https://crates.io/crates/cupid) crate.
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* Linux/Android:
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* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `riscv{32,64}`, `loongarch64`, `s390x`:
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* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch64`, `s390x`:
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`std_detect` supports these on Linux by querying ELF auxiliary vectors (using `getauxval`
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when available), and if that fails, by querying `/proc/cpuinfo`.
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* `arm64`: partial support for doing run-time feature detection by directly
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querying `mrs` is implemented for Linux >= 4.11, but not enabled by default.
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* `riscv{32,64}`:
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`std_detect` supports these on Linux by querying `riscv_hwprobe`, and
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by querying ELF auxiliary vectors (using `getauxval` when available).
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* FreeBSD:
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* `arm32`, `powerpc64`: `std_detect` supports these on FreeBSD by querying ELF
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@ -37,22 +37,39 @@ features! {
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/// * Zbb: `"zbb"`
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/// * Zbs: `"zbs"`
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/// * C: `"c"`
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/// * Zca: `"zca"`
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/// * Zcd: `"zcd"` (if D is enabled)
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/// * Zcf: `"zcf"` (if F is enabled on RV32)
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/// * D: `"d"`
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/// * F: `"f"`
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/// * M: `"m"`
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/// * Q: `"q"`
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/// * V: `"v"`
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/// * Zve32x: `"zve32x"`
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/// * Zve32f: `"zve32f"`
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/// * Zve64x: `"zve64x"`
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/// * Zve64f: `"zve64f"`
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/// * Zve64d: `"zve64d"`
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/// * Zicboz: `"zicboz"`
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/// * Zicntr: `"zicntr"`
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/// * Zicond: `"zicond"`
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/// * Zicsr: `"zicsr"`
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/// * Zifencei: `"zifencei"`
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/// * Zihintntl: `"zihintntl"`
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/// * Zihintpause: `"zihintpause"`
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/// * Zihpm: `"zihpm"`
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/// * Zimop: `"zimop"`
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/// * Zacas: `"zacas"`
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/// * Zawrs: `"zawrs"`
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/// * Zfa: `"zfa"`
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * Zfinx: `"zfinx"`
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/// * Zdinx: `"zdinx"`
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/// * Zhinx: `"zhinx"`
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/// * Zhinxmin: `"zhinxmin"`
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/// * Zcb: `"zcb"`
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/// * Zcmop: `"zcmop"`
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/// * Zbc: `"zbc"`
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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@ -67,6 +84,24 @@ features! {
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkt: `"zkt"`
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/// * Zvbb: `"zvbb"`
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/// * Zvbc: `"zvbc"`
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/// * Zvfh: `"zvfh"`
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/// * Zvfhmin: `"zvfhmin"`
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/// * Zvkb: `"zvkb"`
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/// * Zvkg: `"zvkg"`
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/// * Zvkn: `"zvkn"`
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/// * Zvkned: `"zvkned"`
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/// * Zvknha: `"zvknha"`
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/// * Zvknhb: `"zvknhb"`
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/// * Zvknc: `"zvknc"`
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/// * Zvkng: `"zvkng"`
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/// * Zvks: `"zvks"`
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/// * Zvksed: `"zvksed"`
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/// * Zvksh: `"zvksh"`
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/// * Zvksc: `"zvksc"`
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/// * Zvksg: `"zvksg"`
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/// * Zvkt: `"zvkt"`
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/// * Ztso: `"ztso"`
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///
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/// There's also bases and extensions marked as standard instruction set,
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@ -87,6 +122,15 @@ features! {
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/// * Svnapot: `"svnapot"`
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/// * Svpbmt: `"svpbmt"`
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/// * Svinval: `"svinval"`
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///
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/// # Performance Hints
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///
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/// The two features below define performance hints for unaligned
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/// scalar/vector memory accesses, respectively. If enabled, it denotes that
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/// corresponding unaligned memory access is reasonably fast.
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///
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/// * `"unaligned-scalar-mem"`
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/// * `"unaligned-vector-mem"`
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#[stable(feature = "riscv_ratified", since = "1.78.0")]
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
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@ -102,6 +146,11 @@ features! {
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without cfg check: true;
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/// RV128I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
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/// Has reasonably performant unaligned scalar
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
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/// Has reasonably performant unaligned vector
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
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without cfg check: true;
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/// "Zicsr" Extension for Control and Status Register (CSR) Instructions
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@ -115,9 +164,21 @@ features! {
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without cfg check: true;
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/// "Zifencei" Extension for Instruction-Fetch Fence
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintntl: "zihintntl";
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without cfg check: true;
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/// "Zihintntl" Extension for Non-Temporal Locality Hints
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
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without cfg check: true;
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/// "Zihintpause" Extension for Pause Hint
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zimop: "zimop";
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without cfg check: true;
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/// "Zimop" Extension for May-Be-Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicboz: "zicboz";
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without cfg check: true;
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/// "Zicboz" Extension for Cache-Block Zero Instruction
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicond: "zicond";
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without cfg check: true;
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/// "Zicond" Extension for Integer Conditional Operations
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
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/// "M" Extension for Integer Multiplication and Division
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@ -128,6 +189,10 @@ features! {
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/// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zaamo: "zaamo";
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/// "Zaamo" Extension for Atomic Memory Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
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/// "Zawrs" Extension for Wait-on-Reservation-Set Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
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/// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
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without cfg check: true;
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/// "Zam" Extension for Misaligned Atomics
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@ -146,6 +211,9 @@ features! {
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/// "Zfh" Extension for Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
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/// "Zfhmin" Extension for Minimal Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfa: "zfa";
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without cfg check: true;
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/// "Zfa" Extension for Additional Floating-Point Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
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/// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
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@ -158,6 +226,21 @@ features! {
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
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/// "C" Extension for Compressed Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zca: "zca";
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without cfg check: true;
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/// "Zca" Compressed Instructions excluding Floating-Point Loads/Stores
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcf: "zcf";
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without cfg check: true;
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/// "Zcf" Compressed Instructions for Single-Precision Floating-Point Loads/Stores on RV32
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcd: "zcd";
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without cfg check: true;
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/// "Zcd" Compressed Instructions for Double-Precision Floating-Point Loads/Stores
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcb: "zcb";
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without cfg check: true;
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/// "Zcb" Simple Code-size Saving Compressed Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcmop: "zcmop";
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without cfg check: true;
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/// "Zcmop" Extension for Compressed May-Be-Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
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without cfg check: true;
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@ -200,6 +283,53 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
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/// "V" Extension for Vector Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
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/// "Zve32x" Vector Extension for Embedded Processors (32-bit+; Integer)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
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/// "Zve32f" Vector Extension for Embedded Processors (32-bit+; with Single-Precision Floating-Point)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
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/// "Zve64x" Vector Extension for Embedded Processors (64-bit+; Integer)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
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/// "Zve64f" Vector Extension for Embedded Processors (64-bit+; with Single-Precision Floating-Point)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
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/// "Zve64d" Vector Extension for Embedded Processors (64-bit+; with Double-Precision Floating-Point)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
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/// "Zvfh" Vector Extension for Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
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/// "Zvfhmin" Vector Extension for Minimal Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
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/// "Zvbb" Extension for Vector Basic Bit-Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
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/// "Zvbc" Extension for Vector Carryless Multiplication
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
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/// "Zvkb" Extension for Vector Cryptography Bit-Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
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/// "Zvkg" Cryptography Extension for Vector GCM/GMAC
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
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/// "Zvkned" Cryptography Extension for NIST Suite: Vector AES Block Cipher
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
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/// "Zvknha" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
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/// "Zvknhb" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256/512)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
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/// "Zvksed" Cryptography Extension for ShangMi Suite: Vector SM4 Block Cipher
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
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/// "Zvksh" Cryptography Extension for ShangMi Suite: Vector SM3 Secure Hash
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
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/// "Zvkn" Cryptography Extension for NIST Algorithm Suite
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
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/// "Zvknc" Cryptography Extension for NIST Algorithm Suite with Carryless Multiply
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
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/// "Zvkng" Cryptography Extension for NIST Algorithm Suite with GCM
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
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/// "Zvks" Cryptography Extension for ShangMi Algorithm Suite
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
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/// "Zvksc" Cryptography Extension for ShangMi Algorithm Suite with Carryless Multiply
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
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/// "Zvksg" Cryptography Extension for ShangMi Algorithm Suite with GCM
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
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/// "Zvkt" Extension for Vector Data-Independent Execution Latency
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
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without cfg check: true;
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@ -1,10 +1,127 @@
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//! Run-time feature detection for RISC-V on Linux.
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//!
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//! On RISC-V, detection using auxv only supports single-letter extensions.
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//! So, we use riscv_hwprobe that supports multi-letter extensions if available.
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//! <https://www.kernel.org/doc/html/latest/arch/riscv/hwprobe.html>
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use core::ptr;
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use super::super::riscv::imply_features;
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use super::auxvec;
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use crate::detect::{Feature, bit, cache};
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/// Read list of supported features from the auxiliary vector.
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// See <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/prctl.h?h=v6.14>
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// for runtime status query constants.
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const PR_RISCV_V_GET_CONTROL: libc::c_int = 70;
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const PR_RISCV_V_VSTATE_CTRL_ON: libc::c_int = 2;
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const PR_RISCV_V_VSTATE_CTRL_CUR_MASK: libc::c_int = 3;
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// See <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwprobe.h?h=v6.14>
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// for riscv_hwprobe struct and hardware probing constants.
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#[repr(C)]
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struct riscv_hwprobe {
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key: i64,
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value: u64,
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}
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#[allow(non_upper_case_globals)]
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const __NR_riscv_hwprobe: libc::c_long = 258;
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const RISCV_HWPROBE_KEY_BASE_BEHAVIOR: i64 = 3;
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const RISCV_HWPROBE_BASE_BEHAVIOR_IMA: u64 = 1 << 0;
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const RISCV_HWPROBE_KEY_IMA_EXT_0: i64 = 4;
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const RISCV_HWPROBE_IMA_FD: u64 = 1 << 0;
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const RISCV_HWPROBE_IMA_C: u64 = 1 << 1;
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const RISCV_HWPROBE_IMA_V: u64 = 1 << 2;
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const RISCV_HWPROBE_EXT_ZBA: u64 = 1 << 3;
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const RISCV_HWPROBE_EXT_ZBB: u64 = 1 << 4;
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const RISCV_HWPROBE_EXT_ZBS: u64 = 1 << 5;
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const RISCV_HWPROBE_EXT_ZICBOZ: u64 = 1 << 6;
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const RISCV_HWPROBE_EXT_ZBC: u64 = 1 << 7;
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const RISCV_HWPROBE_EXT_ZBKB: u64 = 1 << 8;
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const RISCV_HWPROBE_EXT_ZBKC: u64 = 1 << 9;
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const RISCV_HWPROBE_EXT_ZBKX: u64 = 1 << 10;
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const RISCV_HWPROBE_EXT_ZKND: u64 = 1 << 11;
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const RISCV_HWPROBE_EXT_ZKNE: u64 = 1 << 12;
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const RISCV_HWPROBE_EXT_ZKNH: u64 = 1 << 13;
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const RISCV_HWPROBE_EXT_ZKSED: u64 = 1 << 14;
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const RISCV_HWPROBE_EXT_ZKSH: u64 = 1 << 15;
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const RISCV_HWPROBE_EXT_ZKT: u64 = 1 << 16;
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const RISCV_HWPROBE_EXT_ZVBB: u64 = 1 << 17;
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const RISCV_HWPROBE_EXT_ZVBC: u64 = 1 << 18;
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const RISCV_HWPROBE_EXT_ZVKB: u64 = 1 << 19;
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const RISCV_HWPROBE_EXT_ZVKG: u64 = 1 << 20;
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const RISCV_HWPROBE_EXT_ZVKNED: u64 = 1 << 21;
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const RISCV_HWPROBE_EXT_ZVKNHA: u64 = 1 << 22;
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const RISCV_HWPROBE_EXT_ZVKNHB: u64 = 1 << 23;
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const RISCV_HWPROBE_EXT_ZVKSED: u64 = 1 << 24;
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const RISCV_HWPROBE_EXT_ZVKSH: u64 = 1 << 25;
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const RISCV_HWPROBE_EXT_ZVKT: u64 = 1 << 26;
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const RISCV_HWPROBE_EXT_ZFH: u64 = 1 << 27;
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const RISCV_HWPROBE_EXT_ZFHMIN: u64 = 1 << 28;
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const RISCV_HWPROBE_EXT_ZIHINTNTL: u64 = 1 << 29;
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const RISCV_HWPROBE_EXT_ZVFH: u64 = 1 << 30;
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const RISCV_HWPROBE_EXT_ZVFHMIN: u64 = 1 << 31;
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const RISCV_HWPROBE_EXT_ZFA: u64 = 1 << 32;
|
||||
const RISCV_HWPROBE_EXT_ZTSO: u64 = 1 << 33;
|
||||
const RISCV_HWPROBE_EXT_ZACAS: u64 = 1 << 34;
|
||||
const RISCV_HWPROBE_EXT_ZICOND: u64 = 1 << 35;
|
||||
const RISCV_HWPROBE_EXT_ZIHINTPAUSE: u64 = 1 << 36;
|
||||
const RISCV_HWPROBE_EXT_ZVE32X: u64 = 1 << 37;
|
||||
const RISCV_HWPROBE_EXT_ZVE32F: u64 = 1 << 38;
|
||||
const RISCV_HWPROBE_EXT_ZVE64X: u64 = 1 << 39;
|
||||
const RISCV_HWPROBE_EXT_ZVE64F: u64 = 1 << 40;
|
||||
const RISCV_HWPROBE_EXT_ZVE64D: u64 = 1 << 41;
|
||||
const RISCV_HWPROBE_EXT_ZIMOP: u64 = 1 << 42;
|
||||
const RISCV_HWPROBE_EXT_ZCA: u64 = 1 << 43;
|
||||
const RISCV_HWPROBE_EXT_ZCB: u64 = 1 << 44;
|
||||
const RISCV_HWPROBE_EXT_ZCD: u64 = 1 << 45;
|
||||
const RISCV_HWPROBE_EXT_ZCF: u64 = 1 << 46;
|
||||
const RISCV_HWPROBE_EXT_ZCMOP: u64 = 1 << 47;
|
||||
const RISCV_HWPROBE_EXT_ZAWRS: u64 = 1 << 48;
|
||||
// Excluded because it only reports the existence of `prctl`-based pointer masking control.
|
||||
// const RISCV_HWPROBE_EXT_SUPM: u64 = 1 << 49;
|
||||
|
||||
const RISCV_HWPROBE_KEY_CPUPERF_0: i64 = 5;
|
||||
const RISCV_HWPROBE_MISALIGNED_FAST: u64 = 3;
|
||||
const RISCV_HWPROBE_MISALIGNED_MASK: u64 = 7;
|
||||
|
||||
const RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF: i64 = 9;
|
||||
const RISCV_HWPROBE_MISALIGNED_SCALAR_FAST: u64 = 3;
|
||||
|
||||
const RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF: i64 = 10;
|
||||
const RISCV_HWPROBE_MISALIGNED_VECTOR_FAST: u64 = 3;
|
||||
|
||||
// syscall returns an unsupported error if riscv_hwprobe is not supported,
|
||||
// so we can safely use this function on older versions of Linux.
|
||||
fn _riscv_hwprobe(out: &mut [riscv_hwprobe]) -> bool {
|
||||
unsafe fn __riscv_hwprobe(
|
||||
pairs: *mut riscv_hwprobe,
|
||||
pair_count: libc::size_t,
|
||||
cpu_set_size: libc::size_t,
|
||||
cpus: *mut libc::c_ulong,
|
||||
flags: libc::c_uint,
|
||||
) -> libc::c_long {
|
||||
unsafe {
|
||||
libc::syscall(
|
||||
__NR_riscv_hwprobe,
|
||||
pairs,
|
||||
pair_count,
|
||||
cpu_set_size,
|
||||
cpus,
|
||||
flags,
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
let len = out.len();
|
||||
unsafe { __riscv_hwprobe(out.as_mut_ptr(), len, 0, ptr::null_mut(), 0) == 0 }
|
||||
}
|
||||
|
||||
/// Read list of supported features from (1) the auxiliary vector
|
||||
/// and (2) the results of `riscv_hwprobe` and `prctl` system calls.
|
||||
pub(crate) fn detect_features() -> cache::Initializer {
|
||||
let mut value = cache::Initializer::default();
|
||||
let mut enable_feature = |feature, enable| {
|
||||
@ -18,6 +135,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
|
||||
//
|
||||
// [hwcap]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwcap.h?h=v6.14
|
||||
let auxv = auxvec::auxv().expect("read auxvec"); // should not fail on RISC-V platform
|
||||
let mut has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
|
||||
#[allow(clippy::eq_op)]
|
||||
enable_feature(Feature::a, bit::test(auxv.hwcap, (b'a' - b'a').into()));
|
||||
enable_feature(Feature::c, bit::test(auxv.hwcap, (b'c' - b'a').into()));
|
||||
@ -25,9 +143,167 @@ pub(crate) fn detect_features() -> cache::Initializer {
|
||||
enable_feature(Feature::f, bit::test(auxv.hwcap, (b'f' - b'a').into()));
|
||||
enable_feature(Feature::h, bit::test(auxv.hwcap, (b'h' - b'a').into()));
|
||||
enable_feature(Feature::m, bit::test(auxv.hwcap, (b'm' - b'a').into()));
|
||||
let has_v = bit::test(auxv.hwcap, (b'v' - b'a').into());
|
||||
let mut is_v_set = false;
|
||||
|
||||
// Use riscv_hwprobe syscall to query more extensions and
|
||||
// performance-related capabilities.
|
||||
'hwprobe: {
|
||||
let mut out = [
|
||||
riscv_hwprobe {
|
||||
key: RISCV_HWPROBE_KEY_BASE_BEHAVIOR,
|
||||
value: 0,
|
||||
},
|
||||
riscv_hwprobe {
|
||||
key: RISCV_HWPROBE_KEY_IMA_EXT_0,
|
||||
value: 0,
|
||||
},
|
||||
riscv_hwprobe {
|
||||
key: RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF,
|
||||
value: 0,
|
||||
},
|
||||
riscv_hwprobe {
|
||||
key: RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF,
|
||||
value: 0,
|
||||
},
|
||||
riscv_hwprobe {
|
||||
key: RISCV_HWPROBE_KEY_CPUPERF_0,
|
||||
value: 0,
|
||||
},
|
||||
];
|
||||
if !_riscv_hwprobe(&mut out) {
|
||||
break 'hwprobe;
|
||||
}
|
||||
|
||||
// Query scalar/vector misaligned behavior.
|
||||
if out[2].key != -1 {
|
||||
enable_feature(
|
||||
Feature::unaligned_scalar_mem,
|
||||
out[2].value == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST,
|
||||
);
|
||||
} else if out[4].key != -1 {
|
||||
// Deprecated method for fallback
|
||||
enable_feature(
|
||||
Feature::unaligned_scalar_mem,
|
||||
out[4].value & RISCV_HWPROBE_MISALIGNED_MASK == RISCV_HWPROBE_MISALIGNED_FAST,
|
||||
);
|
||||
}
|
||||
if out[3].key != -1 {
|
||||
enable_feature(
|
||||
Feature::unaligned_vector_mem,
|
||||
out[3].value == RISCV_HWPROBE_MISALIGNED_VECTOR_FAST,
|
||||
);
|
||||
}
|
||||
|
||||
// Query whether "I" base and extensions "M" and "A" (as in the ISA
|
||||
// manual version 2.2) are enabled. "I" base at that time corresponds
|
||||
// to "I", "Zicsr", "Zicntr" and "Zifencei" (as in the ISA manual version
|
||||
// 20240411) and we chose to imply "Zicsr" and "Zifencei" (not "Zicntr")
|
||||
// because there will be a separate RISCV_HWPROBE_EXT_ZICNTR constant to
|
||||
// determine existence of the "Zicntr" extension in Linux 6.15 (as of rc1).
|
||||
// "fence.i" ("Zifencei") is conditionally valid on the Linux userland
|
||||
// (when CMODX is enabled).
|
||||
// This is a requirement of `RISCV_HWPROBE_KEY_IMA_EXT_0`-based tests.
|
||||
let has_ima = (out[0].key != -1) && (out[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA != 0);
|
||||
if !has_ima {
|
||||
break 'hwprobe;
|
||||
}
|
||||
has_i |= has_ima;
|
||||
enable_feature(Feature::zicsr, has_ima);
|
||||
enable_feature(Feature::zifencei, has_ima);
|
||||
enable_feature(Feature::m, has_ima);
|
||||
enable_feature(Feature::a, has_ima);
|
||||
|
||||
// Enable features based on `RISCV_HWPROBE_KEY_IMA_EXT_0`.
|
||||
if out[1].key == -1 {
|
||||
break 'hwprobe;
|
||||
}
|
||||
let ima_ext_0 = out[1].value;
|
||||
let test = |mask| (ima_ext_0 & mask) != 0;
|
||||
|
||||
enable_feature(Feature::d, test(RISCV_HWPROBE_IMA_FD)); // F is implied.
|
||||
enable_feature(Feature::c, test(RISCV_HWPROBE_IMA_C));
|
||||
|
||||
enable_feature(Feature::zihintntl, test(RISCV_HWPROBE_EXT_ZIHINTNTL));
|
||||
enable_feature(Feature::zihintpause, test(RISCV_HWPROBE_EXT_ZIHINTPAUSE));
|
||||
enable_feature(Feature::zimop, test(RISCV_HWPROBE_EXT_ZIMOP));
|
||||
enable_feature(Feature::zicboz, test(RISCV_HWPROBE_EXT_ZICBOZ));
|
||||
enable_feature(Feature::zicond, test(RISCV_HWPROBE_EXT_ZICOND));
|
||||
|
||||
enable_feature(Feature::zawrs, test(RISCV_HWPROBE_EXT_ZAWRS));
|
||||
enable_feature(Feature::zacas, test(RISCV_HWPROBE_EXT_ZACAS));
|
||||
enable_feature(Feature::ztso, test(RISCV_HWPROBE_EXT_ZTSO));
|
||||
|
||||
enable_feature(Feature::zba, test(RISCV_HWPROBE_EXT_ZBA));
|
||||
enable_feature(Feature::zbb, test(RISCV_HWPROBE_EXT_ZBB));
|
||||
enable_feature(Feature::zbs, test(RISCV_HWPROBE_EXT_ZBS));
|
||||
enable_feature(Feature::zbc, test(RISCV_HWPROBE_EXT_ZBC));
|
||||
|
||||
enable_feature(Feature::zbkb, test(RISCV_HWPROBE_EXT_ZBKB));
|
||||
enable_feature(Feature::zbkc, test(RISCV_HWPROBE_EXT_ZBKC));
|
||||
enable_feature(Feature::zbkx, test(RISCV_HWPROBE_EXT_ZBKX));
|
||||
enable_feature(Feature::zknd, test(RISCV_HWPROBE_EXT_ZKND));
|
||||
enable_feature(Feature::zkne, test(RISCV_HWPROBE_EXT_ZKNE));
|
||||
enable_feature(Feature::zknh, test(RISCV_HWPROBE_EXT_ZKNH));
|
||||
enable_feature(Feature::zksed, test(RISCV_HWPROBE_EXT_ZKSED));
|
||||
enable_feature(Feature::zksh, test(RISCV_HWPROBE_EXT_ZKSH));
|
||||
enable_feature(Feature::zkt, test(RISCV_HWPROBE_EXT_ZKT));
|
||||
|
||||
enable_feature(Feature::zcmop, test(RISCV_HWPROBE_EXT_ZCMOP));
|
||||
enable_feature(Feature::zca, test(RISCV_HWPROBE_EXT_ZCA));
|
||||
enable_feature(Feature::zcf, test(RISCV_HWPROBE_EXT_ZCF));
|
||||
enable_feature(Feature::zcd, test(RISCV_HWPROBE_EXT_ZCD));
|
||||
enable_feature(Feature::zcb, test(RISCV_HWPROBE_EXT_ZCB));
|
||||
|
||||
enable_feature(Feature::zfh, test(RISCV_HWPROBE_EXT_ZFH));
|
||||
enable_feature(Feature::zfhmin, test(RISCV_HWPROBE_EXT_ZFHMIN));
|
||||
enable_feature(Feature::zfa, test(RISCV_HWPROBE_EXT_ZFA));
|
||||
|
||||
// Use prctl (if any) to determine whether the vector extension
|
||||
// is enabled on the current thread (assuming the entire process
|
||||
// share the same status). If prctl fails (e.g. QEMU userland emulator
|
||||
// as of version 9.2.3), use auxiliary vector to retrieve the default
|
||||
// vector status on the process startup.
|
||||
let has_vectors = {
|
||||
let v_status = unsafe { libc::prctl(PR_RISCV_V_GET_CONTROL) };
|
||||
if v_status >= 0 {
|
||||
(v_status & PR_RISCV_V_VSTATE_CTRL_CUR_MASK) == PR_RISCV_V_VSTATE_CTRL_ON
|
||||
} else {
|
||||
has_v
|
||||
}
|
||||
};
|
||||
if has_vectors {
|
||||
enable_feature(Feature::v, test(RISCV_HWPROBE_IMA_V));
|
||||
enable_feature(Feature::zve32x, test(RISCV_HWPROBE_EXT_ZVE32X));
|
||||
enable_feature(Feature::zve32f, test(RISCV_HWPROBE_EXT_ZVE32F));
|
||||
enable_feature(Feature::zve64x, test(RISCV_HWPROBE_EXT_ZVE64X));
|
||||
enable_feature(Feature::zve64f, test(RISCV_HWPROBE_EXT_ZVE64F));
|
||||
enable_feature(Feature::zve64d, test(RISCV_HWPROBE_EXT_ZVE64D));
|
||||
|
||||
enable_feature(Feature::zvbb, test(RISCV_HWPROBE_EXT_ZVBB));
|
||||
enable_feature(Feature::zvbc, test(RISCV_HWPROBE_EXT_ZVBC));
|
||||
enable_feature(Feature::zvkb, test(RISCV_HWPROBE_EXT_ZVKB));
|
||||
enable_feature(Feature::zvkg, test(RISCV_HWPROBE_EXT_ZVKG));
|
||||
enable_feature(Feature::zvkned, test(RISCV_HWPROBE_EXT_ZVKNED));
|
||||
enable_feature(Feature::zvknha, test(RISCV_HWPROBE_EXT_ZVKNHA));
|
||||
enable_feature(Feature::zvknhb, test(RISCV_HWPROBE_EXT_ZVKNHB));
|
||||
enable_feature(Feature::zvksed, test(RISCV_HWPROBE_EXT_ZVKSED));
|
||||
enable_feature(Feature::zvksh, test(RISCV_HWPROBE_EXT_ZVKSH));
|
||||
enable_feature(Feature::zvkt, test(RISCV_HWPROBE_EXT_ZVKT));
|
||||
|
||||
enable_feature(Feature::zvfh, test(RISCV_HWPROBE_EXT_ZVFH));
|
||||
enable_feature(Feature::zvfhmin, test(RISCV_HWPROBE_EXT_ZVFHMIN));
|
||||
}
|
||||
is_v_set = true;
|
||||
};
|
||||
|
||||
// Set V purely depending on the auxiliary vector
|
||||
// only if no fine-grained vector extension detection is available.
|
||||
if !is_v_set {
|
||||
enable_feature(Feature::v, has_v);
|
||||
}
|
||||
|
||||
// Handle base ISA.
|
||||
let has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
|
||||
// If future RV128I is supported, implement with `enable_feature` here.
|
||||
// Note that we should use `target_arch` instead of `target_pointer_width`
|
||||
// to avoid misdetection caused by experimental ABIs such as RV64ILP32.
|
||||
|
||||
@ -62,25 +62,67 @@ pub(crate) fn imply_features(mut value: cache::Initializer) -> cache::Initialize
|
||||
"defined as subset":
|
||||
The latter extension is described as a subset of the former
|
||||
(but the evidence is weak).
|
||||
"functional":
|
||||
The former extension is functionally a superset of the latter
|
||||
(no direct references though).
|
||||
*/
|
||||
|
||||
imply!(zvbb => zvkb);
|
||||
|
||||
// Certain set of vector cryptography extensions form a group.
|
||||
group!(zvkn == zvkned & zvknhb & zvkb & zvkt);
|
||||
group!(zvknc == zvkn & zvbc);
|
||||
group!(zvkng == zvkn & zvkg);
|
||||
group!(zvks == zvksed & zvksh & zvkb & zvkt);
|
||||
group!(zvksc == zvks & zvbc);
|
||||
group!(zvksg == zvks & zvkg);
|
||||
|
||||
imply!(zvknhb => zvknha); // functional
|
||||
|
||||
// For vector cryptography, Zvknhb and Zvbc require integer arithmetic
|
||||
// with EEW=64 (Zve64x) while others not depending on them
|
||||
// require EEW=32 (Zve32x).
|
||||
imply!(zvknhb | zvbc => zve64x);
|
||||
imply!(zvbb | zvkb | zvkg | zvkned | zvknha | zvksed | zvksh => zve32x);
|
||||
|
||||
imply!(zbc => zbkc); // defined as subset
|
||||
group!(zkn == zbkb & zbkc & zbkx & zkne & zknd & zknh);
|
||||
group!(zks == zbkb & zbkc & zbkx & zksed & zksh);
|
||||
group!(zk == zkn & zkr & zkt);
|
||||
|
||||
imply!(zacas => zaamo);
|
||||
group!(a == zalrsc & zaamo);
|
||||
|
||||
group!(b == zba & zbb & zbs);
|
||||
|
||||
imply!(zcf => zca & f);
|
||||
imply!(zcd => zca & d);
|
||||
imply!(zcmop | zcb => zca);
|
||||
|
||||
imply!(zhinx => zhinxmin);
|
||||
imply!(zdinx | zhinxmin => zfinx);
|
||||
|
||||
imply!(zvfh => zvfhmin); // functional
|
||||
imply!(zvfh => zve32f & zfhmin);
|
||||
imply!(zvfhmin => zve32f);
|
||||
|
||||
imply!(v => zve64d);
|
||||
imply!(zve64d => zve64f & d);
|
||||
imply!(zve64f => zve64x & zve32f);
|
||||
imply!(zve64x => zve32x);
|
||||
imply!(zve32f => zve32x & f);
|
||||
|
||||
imply!(zfh => zfhmin);
|
||||
imply!(q => d);
|
||||
imply!(d | zfhmin => f);
|
||||
imply!(d | zfhmin | zfa => f);
|
||||
|
||||
imply!(zicntr | zihpm | f | zfinx => zicsr);
|
||||
// Relatively complex implication rules from the "C" extension.
|
||||
imply!(c => zca);
|
||||
imply!(c & d => zcd);
|
||||
#[cfg(target_arch = "riscv32")]
|
||||
imply!(c & f => zcf);
|
||||
|
||||
imply!(zicntr | zihpm | f | zfinx | zve32x => zicsr);
|
||||
imply!(s | h => zicsr);
|
||||
|
||||
// Loop until the feature flags converge.
|
||||
@ -110,6 +152,16 @@ mod tests {
|
||||
assert!(imply_features(value).test(Feature::zicsr as u32));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn complex_zcd() {
|
||||
let mut value = cache::Initializer::default();
|
||||
// C & D -> Zcd
|
||||
value.set(Feature::c as u32);
|
||||
assert!(!imply_features(value).test(Feature::zcd as u32));
|
||||
value.set(Feature::d as u32);
|
||||
assert!(imply_features(value).test(Feature::zcd as u32));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn group_simple_forward() {
|
||||
let mut value = cache::Initializer::default();
|
||||
@ -132,17 +184,18 @@ mod tests {
|
||||
#[test]
|
||||
fn group_complex_convergence() {
|
||||
let mut value = cache::Initializer::default();
|
||||
// Needs 2 iterations to converge
|
||||
// (and 3rd iteration for convergence checking):
|
||||
// 1. [Zk] -> Zkn & Zkr & Zkt
|
||||
// 2. Zkn -> {Zbkb} & {Zbkc} & {Zbkx} & {Zkne} & {Zknd} & {Zknh}
|
||||
value.set(Feature::zk as u32);
|
||||
// Needs 3 iterations to converge
|
||||
// (and 4th iteration for convergence checking):
|
||||
// 1. [Zvksc] -> Zvks & Zvbc
|
||||
// 2. Zvks -> Zvksed & Zvksh & Zvkb & Zvkt
|
||||
// 3a. [Zvkned] & [Zvknhb] & [Zvkb] & Zvkt -> {Zvkn}
|
||||
// 3b. Zvkn & Zvbc -> {Zvknc}
|
||||
value.set(Feature::zvksc as u32);
|
||||
value.set(Feature::zvkned as u32);
|
||||
value.set(Feature::zvknhb as u32);
|
||||
value.set(Feature::zvkb as u32);
|
||||
let value = imply_features(value);
|
||||
assert!(value.test(Feature::zbkb as u32));
|
||||
assert!(value.test(Feature::zbkc as u32));
|
||||
assert!(value.test(Feature::zbkx as u32));
|
||||
assert!(value.test(Feature::zkne as u32));
|
||||
assert!(value.test(Feature::zknd as u32));
|
||||
assert!(value.test(Feature::zknh as u32));
|
||||
assert!(value.test(Feature::zvkn as u32));
|
||||
assert!(value.test(Feature::zvknc as u32));
|
||||
}
|
||||
}
|
||||
|
||||
@ -236,15 +236,29 @@ fn riscv_linux() {
|
||||
println!("rv32e: {}", is_riscv_feature_detected!("rv32e"));
|
||||
println!("rv64i: {}", is_riscv_feature_detected!("rv64i"));
|
||||
println!("rv128i: {}", is_riscv_feature_detected!("rv128i"));
|
||||
println!(
|
||||
"unaligned-scalar-mem: {}",
|
||||
is_riscv_feature_detected!("unaligned-scalar-mem")
|
||||
);
|
||||
println!(
|
||||
"unaligned-vector-mem: {}",
|
||||
is_riscv_feature_detected!("unaligned-vector-mem")
|
||||
);
|
||||
println!("zicsr: {}", is_riscv_feature_detected!("zicsr"));
|
||||
println!("zicntr: {}", is_riscv_feature_detected!("zicntr"));
|
||||
println!("zihpm: {}", is_riscv_feature_detected!("zihpm"));
|
||||
println!("zifencei: {}", is_riscv_feature_detected!("zifencei"));
|
||||
println!("zihintntl: {}", is_riscv_feature_detected!("zihintntl"));
|
||||
println!("zihintpause: {}", is_riscv_feature_detected!("zihintpause"));
|
||||
println!("zimop: {}", is_riscv_feature_detected!("zimop"));
|
||||
println!("zicboz: {}", is_riscv_feature_detected!("zicboz"));
|
||||
println!("zicond: {}", is_riscv_feature_detected!("zicond"));
|
||||
println!("m: {}", is_riscv_feature_detected!("m"));
|
||||
println!("a: {}", is_riscv_feature_detected!("a"));
|
||||
println!("zalrsc: {}", is_riscv_feature_detected!("zalrsc"));
|
||||
println!("zaamo: {}", is_riscv_feature_detected!("zaamo"));
|
||||
println!("zawrs: {}", is_riscv_feature_detected!("zawrs"));
|
||||
println!("zacas: {}", is_riscv_feature_detected!("zacas"));
|
||||
println!("zam: {}", is_riscv_feature_detected!("zam"));
|
||||
println!("ztso: {}", is_riscv_feature_detected!("ztso"));
|
||||
println!("f: {}", is_riscv_feature_detected!("f"));
|
||||
@ -252,11 +266,17 @@ fn riscv_linux() {
|
||||
println!("q: {}", is_riscv_feature_detected!("q"));
|
||||
println!("zfh: {}", is_riscv_feature_detected!("zfh"));
|
||||
println!("zfhmin: {}", is_riscv_feature_detected!("zfhmin"));
|
||||
println!("zfa: {}", is_riscv_feature_detected!("zfa"));
|
||||
println!("zfinx: {}", is_riscv_feature_detected!("zfinx"));
|
||||
println!("zdinx: {}", is_riscv_feature_detected!("zdinx"));
|
||||
println!("zhinx: {}", is_riscv_feature_detected!("zhinx"));
|
||||
println!("zhinxmin: {}", is_riscv_feature_detected!("zhinxmin"));
|
||||
println!("c: {}", is_riscv_feature_detected!("c"));
|
||||
println!("zca: {}", is_riscv_feature_detected!("zca"));
|
||||
println!("zcf: {}", is_riscv_feature_detected!("zcf"));
|
||||
println!("zcd: {}", is_riscv_feature_detected!("zcd"));
|
||||
println!("zcb: {}", is_riscv_feature_detected!("zcb"));
|
||||
println!("zcmop: {}", is_riscv_feature_detected!("zcmop"));
|
||||
println!("b: {}", is_riscv_feature_detected!("b"));
|
||||
println!("zba: {}", is_riscv_feature_detected!("zba"));
|
||||
println!("zbb: {}", is_riscv_feature_detected!("zbb"));
|
||||
@ -276,6 +296,29 @@ fn riscv_linux() {
|
||||
println!("zk: {}", is_riscv_feature_detected!("zk"));
|
||||
println!("zkt: {}", is_riscv_feature_detected!("zkt"));
|
||||
println!("v: {}", is_riscv_feature_detected!("v"));
|
||||
println!("zve32x: {}", is_riscv_feature_detected!("zve32x"));
|
||||
println!("zve32f: {}", is_riscv_feature_detected!("zve32f"));
|
||||
println!("zve64x: {}", is_riscv_feature_detected!("zve64x"));
|
||||
println!("zve64f: {}", is_riscv_feature_detected!("zve64f"));
|
||||
println!("zve64d: {}", is_riscv_feature_detected!("zve64d"));
|
||||
println!("zvfh: {}", is_riscv_feature_detected!("zvfh"));
|
||||
println!("zvfhmin: {}", is_riscv_feature_detected!("zvfhmin"));
|
||||
println!("zvbb: {}", is_riscv_feature_detected!("zvbb"));
|
||||
println!("zvbc: {}", is_riscv_feature_detected!("zvbc"));
|
||||
println!("zvkb: {}", is_riscv_feature_detected!("zvkb"));
|
||||
println!("zvkg: {}", is_riscv_feature_detected!("zvkg"));
|
||||
println!("zvkned: {}", is_riscv_feature_detected!("zvkned"));
|
||||
println!("zvknha: {}", is_riscv_feature_detected!("zvknha"));
|
||||
println!("zvknhb: {}", is_riscv_feature_detected!("zvknhb"));
|
||||
println!("zvksed: {}", is_riscv_feature_detected!("zvksed"));
|
||||
println!("zvksh: {}", is_riscv_feature_detected!("zvksh"));
|
||||
println!("zvkn: {}", is_riscv_feature_detected!("zvkn"));
|
||||
println!("zvknc: {}", is_riscv_feature_detected!("zvknc"));
|
||||
println!("zvkng: {}", is_riscv_feature_detected!("zvkng"));
|
||||
println!("zvks: {}", is_riscv_feature_detected!("zvks"));
|
||||
println!("zvksc: {}", is_riscv_feature_detected!("zvksc"));
|
||||
println!("zvksg: {}", is_riscv_feature_detected!("zvksg"));
|
||||
println!("zvkt: {}", is_riscv_feature_detected!("zvkt"));
|
||||
println!("svnapot: {}", is_riscv_feature_detected!("svnapot"));
|
||||
println!("svpbmt: {}", is_riscv_feature_detected!("svpbmt"));
|
||||
println!("svinval: {}", is_riscv_feature_detected!("svinval"));
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user