itsscb/rust
1
0
Fork 0
mirror of https://github.com/rust-lang/rust.git synced 2025-11-03 14:34:58 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,708 Commits 10 Branches 150 Tags
Commit Graph

1701 Commits

Author SHA1 Message Date
Eduardo Sánchez Muñoz
02bdadb2ae Add parentheses to avoid (re)parsing ambiguity in test_vsri macro. 2023-10-02 21:29:51 +01:00
Eduardo Sánchez Muñoz
95d83fd436 Add #[cfg_attr(miri, ignore)] to SSE and SSE2 that cannot be supported by Miri 2023-10-02 21:29:51 +01:00
Eduardo Sánchez Muñoz
41dc4aad89 Support adding attributes to simd_test tests 
It uses the syn crate to parse the function, so the name can now be extracted without the `find_name` helper.
 2023-10-02 21:29:51 +01:00
Eduardo Sánchez Muñoz
b8b79f2e7a Avoid subtraction overflow in test_mm_store{,1,r}_ps functions 
This overflow was found while testing core_arch with miri
 2023-10-02 21:29:51 +01:00
Eduardo Sánchez Muñoz
fe8004cd5e Use assert_approx_eq! in test_mm_rcp_ss 
Like done in `test_mm_rcp_ps`, but only for the first element.
 2023-10-02 21:29:51 +01:00
Eduardo Sánchez Muñoz
69ff2e3a37 Explicitly disable SSE3 for x86_64 2023-10-01 17:57:00 +01:00
Eduardo Sánchez Muñoz
30a663b4ac Add some #[allow(deprecated)] 2023-10-01 17:57:00 +01:00
Eduardo Sánchez Muñoz
83668823fd Remove references to _mm_getcsr or _mm_setcsr in other function's docs 2023-10-01 17:57:00 +01:00
Eduardo Sánchez Muñoz
a601d109b4 Deprecate functions that use _mm_getcsr or _mm_setcsr 2023-10-01 17:57:00 +01:00
Ralf Jung
5acb9a26e7 deprecate _mm_getcsr and _mm_setcsr 2023-09-29 09:45:50 +01:00
Ralf Jung
08652d6d6b another typo 2023-09-29 09:45:50 +01:00
Ralf Jung
7d5ffdffd7 fix typo 
Co-authored-by: Jacob Lifshay <programmerjake@gmail.com>
 2023-09-29 09:45:50 +01:00
Ralf Jung
06f5033e50 Rust does not let you observe or mutate the floating-point register in well-defined ways 2023-09-29 09:45:50 +01:00
Taiki Endo
059b848b8a core_arch: Fix ARMv6 CP15 barrier 2023-09-29 09:10:33 +01:00
Gijs Burghoorn
73a820bc6b Add missing aes64im of RISC-V Zk extension 2023-09-25 10:36:24 +08:00
Gijs Burghoorn
0d56394f35 Fix: #1464 for rv64 zb 2023-09-22 10:08:56 +08:00
Gijs Burghoorn
8a23f93e8b Fix: #1464 for rv64 zk 2023-09-22 10:08:56 +08:00
Eduardo Sánchez Muñoz
bc7c676407 Format 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
4551a9acab Improve _mm_max_ps, _mm_min_pd, _mm_max_pd tests 
Includes cases to test -0.0, like done for `_mm_min_ps`.
 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
26425131b6 Improve SSE2 slli/srli/srai tests 
Includes cases where the shift amount is equal to the number of bits
 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
bb0d9a41e1 Improve SSE2 sll/srl/sra tests 
Includes cases where the shift amount is equal or greater to the number of bits.
 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
f056604ac2 Add #[track_caller] to assert_eq_* functions 2023-09-22 10:07:29 +08:00
Gijs Burghoorn
dd2d469c8b Impr: Add a usage check for the ci/run-docker.sh script 2023-09-01 21:43:29 +02:00
Gijs Burghoorn
f4ee8f0282 Fix: Testing for RISC-V Zb intrinsics 2023-09-01 18:32:40 +02:00
Gijs Burghoorn
c460cf6706 Impl: Add RISC-V Zb intrinsics 2023-09-01 18:32:40 +02:00
Gijs Burghoorn
d1229d008b Fix: Add proper flags for RISCV64 ci 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
4be26a9497 Fix: Remove assert_instr for RISCV, see #1464 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
f669624b6f Fix: Add constant for assert_instr 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
0b5a5ce567 Fix: Remove unused arch::asm imports 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
cf14e15b7f Impr: Remove pack instructions as instrinsics 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
164af4a836 Chore: Cargo format 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
0e0a78a3f0 Fix: Utilize LLVM intrinsics where possible 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
7fd998870d Fix: Change to 'rustc_legacy_const_generics' 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
992bd5e1a9 Fix: Assembly mistakes in RISC-V Zk extensions 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
1c5eb32416 Chore cargo fmt 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
f0be271de9 Implement RISC-V Zk extension intrinsics 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
e301d8bba4 Depend on riscv_ext_intrinsics feature. 2023-08-31 23:12:32 +02:00
Eduardo Sánchez Muñoz
877098179a Fix _mm_srli_epi64 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
7f5b70be72 Implement AVX512BW 16-bit shift by immediate (srai_epi16) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
427bb149f0 Implement AVX512BW 16-bit shift by immediate (srli_epi16) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
0c0f72ee7f Implement AVX512BW 16-bit shift by immediate (slli_epi16) with simd_shl instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
4b2efda9a9 Implement AVX512F 64-bit shift by immediate (srai_epi64) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
01ff55e216 Implement AVX512F 32-bit shift by immediate (srai_epi32) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
29ba594589 Implement AVX512F 64-bit shift by immediate (srli_epi64) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
c3fdf91585 Implement AVX512F 32-bit shift by immediate (srli_epi32) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
25a978a69f Implement AVX512F 64-bit shift by immediate (slli_epi64) with simd_shl instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
bf3a28f6ad Implement AVX512F 32-bit shift by immediate (slli_epi32) with simd_shl instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
f942d69471 Implement AVX2 shift by immediate (slli, srli, srai) with simd_sh{l,r} instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
819fe11c49 Implement SSE2 shift by immediate (slli, srli, srai) with simd_sh{l,r} instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
3b7dc00f66 Implement SSE2 and AVX unaligned stores (storeu) with <*mut T>::write_unaligned instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00