Implement the MCP 932: Promote riscv64a23-unknown-linux-gnu to Tier 2
Implement the [MCP 932](https://github.com/rust-lang/compiler-team/issues/932): Promote riscv64a23-unknown-linux-gnu to Tier 2 without host tools.
Closesrust-lang/rust#148353.
Changes:
- Update target tier from 3 to 2 in target specification
- Update platform documentation
- Add CI/CD support for automatic building and distribution via rustup
r? jieyouxu
cc `@davidtwco` `@Noratrieb`
Add LLVM realtime sanitizer
This is a new attempt at adding the [LLVM real-time sanitizer](https://clang.llvm.org/docs/RealtimeSanitizer.html) to rust.
Previously this was attempted in https://github.com/rust-lang/rfcs/pull/3766.
Since then the `sanitize` attribute was introduced in https://github.com/rust-lang/rust/pull/142681 and it is a lot more flexible than the old `no_santize` attribute. This allows adding real-time sanitizer without the need for a new attribute, like it was proposed in the RFC. Because i only add a new value to a existing command line flag and to a attribute i don't think an MCP is necessary.
Currently real-time santizer is usable in rust code with the [rtsan-standalone](https://crates.io/crates/rtsan-standalone) crate. This downloads or builds the sanitizer runtime and then links it into the rust binary.
The first commit adds support for more detailed sanitizer information.
The second commit then actually adds real-time sanitizer.
The third adds a warning against using real-time sanitizer with async functions, cloures and blocks because it doesn't behave as expected when used with async functions. I am not sure if this is actually wanted, so i kept it in a seperate commit.
The fourth commit adds the documentation for real-time sanitizer.
Offload device
LLVM's offload functionality usually expects an extra dyn_ptr argument. We could avoid it,b ut likely gonna need it very soon in one of the follow-up PRs (e.g. to request shared memory). So we might as well already add it.
This PR adds a %dyn_ptr ptr to GPUKernel ABI functions, if the offload feature is enabled.
WIP
r? ```@ghost```
Add default sanitizers to TargetOptions
Some sanitizers are part of a system's ABI, like the shadow call stack on Aarch64 and RISC-V Fuchsia. Typically ABI options have other spellings, but LLVM has, for historical reasons, marked this as a sanitizer instead of an alternate ABI option. As a result, Fuchsia targets may not be compiled against the correct ABI unless this option is set. This hasn't caused correctness problems, since the backend reserves the SCS register, and thus preserves its value. But this is an issue for unwinding, as the SCS will not be an array of PCs describing the call complete call chain, and will have gaps from callers that don't use the correct ABI.
In the long term, I'd like to see all the sanitizer configs that all frontends copy from clang moved into llvm's libFrontend, and exposed so that frontend consumers can use a small set of simple APIs to use sanitizers in a consistent way across the LLVM ecosystem, but that work is not yet ready today.
Unify the configuration of the compiler docs
Previously it was rather inconsistent which crates got the rust logo and which didn't and setting html_root_url was forgotten in many cases.
Relax r29 inline asm restriction on PowerPC64 targets
LLVM uses r29 to hold a base pointer for some PowerPC target configurations. It is usable on all 64 bit targets as a callee save register.
r? `@Amanieu`
Stabilize `fmt::from_fn`
Resolvesrust-lang/rust#146705, pending its FCP.
As discussed in that tracking issue and rust-lang/rust#117729, this splits `fmt::from_fn` out from the `debug_closure_helpers` feature.
Some sanitizers are part of a system's ABI, like the shadow call stack
on Aarch64 and RISC-V Fuchsia. Typically ABI options have other
spellings, but LLVM has, for historical reasons, marked this as a
sanitizer instead of an alternate ABI option. As a result, Fuchsia
targets may not be compiled against the correct ABI unless this option
is set. This hasn't caused correctness problems, since the backend
reserves the SCS register, and thus preserves its value. But this is an
issue for unwinding, as the SCS will not be an array of PCs describing
the call complete call chain, and will have gaps from callers that don't
use the correct ABI.
In the long term, I'd like to see all the sanitizer configs that all
frontends copy from clang moved into llvm's libFrontend, and exposed so
that frontend consumers can use a small set of simple APIs to use
sanitizers in a consistent way across the LLVM ecosystem, but that work
is not yet ready today.
Changes:
- Update target tier from 3 to 2 in target specification
- Update platform documentation
- Add CI/CD support for automatic building and distribution via rustup
Rollup of 10 pull requests
Successful merges:
- rust-lang/rust#135602 (Tweak output of missing lifetime on associated type)
- rust-lang/rust#139751 (Implement pin-project in pattern matching for `&pin mut|const T`)
- rust-lang/rust#142682 (Update bundled musl to 1.2.5)
- rust-lang/rust#148171 (Simplify code to generate line numbers in highlight)
- rust-lang/rust#148263 (Unpin `libc` and `rustix` in `compiler` and `rustbook`)
- rust-lang/rust#148301 ([rustdoc search] Include extern crates when filtering on `import`)
- rust-lang/rust#148330 (Don't require dlltool with the dummy backend on MinGW)
- rust-lang/rust#148338 (cleanup: upstream dropped amx-transpose functionality)
- rust-lang/rust#148340 (Clippy subtree update)
- rust-lang/rust#148343 (`nonpoison::Condvar` should take `MutexGuard` by reference)
r? `@ghost`
`@rustbot` modify labels: rollup
cleanup: upstream dropped amx-transpose functionality
See also LLVM change 5322fb626820. Looks like this was just removed entirely.
It seems a little bad to just drop it, but I don't see an easy way to conditionalize
this and if it's really just Gone and we marked it as unstable (which it looks like
we did?) I guess we should just dump it.
````@rustbot```` label llvm-main
Targets theoretically possible, but not provided yet:
- 32-bit arm
See also notes in the PR, I was unable to run anything non-trivial on ARM HelenOS, there are issues
with the linker/loader, incomplete support of atomics, and overall a lot of confusion about
the precise version of ARM architecture that the HelenOS builds target.
- riscv, mips (These targets currently don't run HelenOS at all. HelenOS says it should work, but the builds are broken for quite some time now.)
Align VEX V5 boot routine to 4 bytes
This PR fixes an alignment issue with the initialization routine on the VEX V5 target.
Previously, if the `.text` output section contained any functions aligned to more than four bytes, the linker would add padding bytes before the beginning of `.text` rather than changing the position of the aligned function inside the section itself. This is an issue because the entry point for the program needs to be located at `0x3800_0020` on this platform and the addition of padding could cause it to be moved.
To fix this, I've forced the start address of the `.text` section to be aligned to 4 bytes so that the entry point is placed consistently. Items inside the section can still be aligned to values larger than this.
Extend attribute deduction to determine whether parameters using
indirect pass mode might have their address captured. Similarly to
the deduction of `readonly` attribute this information facilitates
memcpy optimizations.
Fix backtraces with `-C panic=abort` on qnx; emit unwind tables by default
While syncing https://github.com/rust-lang/rust/pull/143613 into Ferrocene as part of https://github.com/ferrocene/ferrocene/pull/1803, we noted a failure on our QNX targets:
```
---- [ui] tests/ui/panics/panic-abort-backtrace-without-debuginfo.rs stdout ----
error: test did not exit with success! code=Some(134) so test would pass with `run-crash`
status: exit status: 134
command: RUSTC="/home/ci/project/build/x86_64-unknown-linux-gnu/stage2/bin/rustc" RUST_TEST_THREADS="1" "/home/ci/project/build/x86_64-unknown-linux-gnu/stage1-tools-bin/remote-test-client" "run" "0" "/home/ci/project/build/x86_64-unknown-linux-gnu/test/ui/panics/panic-abort-backtrace-without-debuginfo/a"
--- stdout -------------------------------
uploaded "/home/ci/project/build/x86_64-unknown-linux-gnu/test/ui/panics/panic-abort-backtrace-without-debuginfo/a", waiting for result
died due to signal 6
------------------------------------------
--- stderr -------------------------------
thread 'main' (1) panicked at /home/ci/project/tests/ui/panics/panic-abort-backtrace-without-debuginfo.rs:39:9:
ERROR: no `this_function_must_be_in_the_backtrace` in stderr! actual stderr:
thread 'main' (1) panicked at /home/ci/project/tests/ui/panics/panic-abort-backtrace-without-debuginfo.rs:27:5:
generate panic backtrace
stack backtrace:
0: 0x4e66a53643 - <std::sys::backtrace::BacktraceLock::print::DisplayBacktrace as core::fmt::Display>::fmt::h55e010263b1e3169
1: 0x4e66a68cd2 - core::fmt::write::h0d6e2e8752abc333
2: 0x4e66a16919 - std::io::Write::write_fmt::h71c4c024d832b384
3: 0x4e66a1f8e2 - std::sys::backtrace::BacktraceLock::print::hdd80dfdf90bb7100
4: 0x4e66a221e0 - std::panicking::default_hook::{{closure}}::h77758f25a686500f
5: 0x4e66a21f69 - std::panicking::default_hook::ha63f7d476af6c267
6: 0x4e66a22999 - std::panicking::panic_with_hook::h3a36a8a0f0dd8ccd
7: 0x4e66a21cac - std::panicking::begin_panic::{{closure}}::h570dedb92e232392
8: 0x4e66a1fa69 - std::sys::backtrace::__rust_end_short_backtrace::h5366eec354f92733
9: 0x4e669f9589 - std::panicking::begin_panic::h04a4bd4c33dd4056
10: 0x4e66a00aca - panic_abort_backtrace_without_debuginfo::and_this_function_too::h5b034b94cbe9c3d3
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
------------------------------------------
---- [ui] tests/ui/panics/panic-abort-backtrace-without-debuginfo.rs stdout end ----
failures:
[ui] tests/ui/panics/panic-abort-backtrace-without-debuginfo.rs
test result: FAILED. 19958 passed; 1 failed; 328 ignored; 0 measured; 0 filtered out; finished in 1827.71s
Some tests failed in compiletest suite=ui mode=ui host=x86_64-unknown-linux-gnu target=x86_64-pc-nto-qnx710
Build completed unsuccessfully in 0:43:28
Exited with code exit status 1
```
This patch applies the same fix as the one found in https://github.com/rust-lang/rust/pull/143613 of adding the `default_uwtable: true` to the target.
I've run it locally, when https://github.com/ferrocene/ferrocene/pull/1803 merges we'll know it has passed within our CI, which is about a close an analog as I can offer to Rust.
Add vsx register support for ppc inline asm, and implement preserves_flag option
This should address the last(?) missing pieces of inline asm for ppc:
* Explicit VSX register support. ISA 2.06 (POWER7) added a 64x128b register overlay extending the fpr's to 128b, and unifies them with the vmx (altivec) registers. Implementations details within gcc/llvm percolate up, and require using the `x` template modifier. I have updated the inline asm to implicitly include this for vsx arguments which do not specify it. ~~Support for the gcc codegen backend is still a todo.~~
* Implement the `preserves_flags` option. All ABI's, and all ISAs store their flags in `cr`, and the carry bit lives inside `xer`. The other status registers hold sticky bits or control bits which do not affect branch instructions.
There is some interest in the e500 (powerpcspe) port. Architecturally, it has a very different FP ISA, and includes a simd extension called SPR (which is not IBM's cell SPE). Notably, it does not have altivec/fpr/vsx registers. It also has an SPE accumulator register which its ABI marks as volatile, but I am not sure if the compiler uses it.
Where supported, VSX is a 64x128b register set which encompasses
both the floating point and vector registers.
In the type tests, xvsqrtdp is used as it is the only two-argument
vsx opcode supported by all targets on llvm. If you need to copy
a vsx register, the preferred way is "xxlor xt, xa, xa".
Generalize configuring LLD as the default linker in bootstrap
Reopen of https://github.com/rust-lang/rust/pull/147157, because apparently bors can't deal with it for some reason.
r? ``@ghost``
Promote armv7a-none-eabihf to Tier 2
This PR promotes armv7a-none-eabihf to Tier 2, to join armv7r-none-eabihf and armv7a-none-eabi. I believe it was simply an oversight that it wasn't made Tier 2 before, as most Armv7-A targets have an FPU and it often makes sense to use it.
This PR wil be rebased once https://github.com/rust-lang/rust/pull/146419 completes the queue.
> - A tier 2 target must have value to people other than its maintainers. (It may
> still be a niche target, but it must not be exclusively useful for an
> inherently closed group.)
The `armv7a-none-eabihf` target is for all Arm Cortex-A processors (either 32-bit only, or in 32-bit mode) where the user wants to use the FPU.
>- A tier 2 target must have a designated team of developers (the "target
> maintainers") available to consult on target-specific build-breaking issues,
> or if necessary to develop target-specific language or library implementation
> details. This team must have at least 2 developers.
The Embedded Devices Working Group's Arm Team have just started maintaining this target.
> - The target must not place undue burden on Rust developers not specifically
> concerned with that target. Rust developers are expected to not gratuitously
> break a tier 2 target, but are not expected to become experts in every tier 2
> target, and are not expected to provide target-specific implementations for
> every tier 2 target.
This target is highly similar to a number of existing Tier 2 targets, including `armv7r-none-eabihf` and `armv7a-none-eabi` and so it should not add undue burden.
> - The target must provide documentation for the Rust community explaining how
> to build for the target using cross-compilation, and explaining how to run
> tests for the target. If at all possible, this documentation should show how
> to run Rust programs and tests for the target using emulation, to allow
> anyone to do so. If the target cannot be feasibly emulated, the documentation
> should explain how to obtain and work with physical hardware, cloud systems,
> or equivalent.
https://doc.rust-lang.org/nightly/rustc/platform-support/armv7a-none-eabi.html was added in https://github.com/rust-lang/rust/pull/146419/. It covers the `-eabi` and the `-eabihf` targets.
> - The target must document its baseline expectations for the features or
> versions of CPUs, operating systems, libraries, runtime environments, and
> similar.
I believe it does.
> - If introducing a new tier 2 or higher target that is identical to an existing
> Rust target except for the baseline expectations for the features or versions
> of CPUs, operating systems, libraries, runtime environments, and similar,
> then the proposed target must document to the satisfaction of the approving
> teams why the specific difference in baseline expectations provides
> sufficient value to justify a separate target.
It uses very similar FPUs to `armv7r-none-eabihf` but is otherwise the same as `armv7a-none-eabi`.
> - Tier 2 targets must not leave any significant portions of `core` or the
> standard library unimplemented or stubbed out, unless they cannot possibly be
> supported on the target.
It has a full libcore, as per the other arm*-none-* targets.
> - The code generation backend for the target should not have deficiencies that
> invalidate Rust safety properties, as evaluated by the Rust compiler team.
It should be the same backend as `armv7r-none-eabihf` and friends, except for FPU support, which is already covered in `thumbv8m.main-none-eabihf`. There are no issues that I know of.
> - If the target supports C code, and the target has an interoperable calling
> convention for C code, the Rust target must support that C calling convention
> for the platform via `extern "C"`. The C calling convention does not need to
> be the default Rust calling convention for the target, however.
The ABI is EABI, the same as many other Arm targets.
> - The target must build reliably in CI, for all components that Rust's CI
> considers mandatory.
The https://github.com/rust-embedded/cortex-ar repository has been changed in https://github.com/rust-embedded/cortex-ar/pull/57 to build this target with `-Zbuild-std=core`. Locally it seems fine.
> - The approving teams may additionally require that a subset of tests pass in
> CI, such as enough to build a functional "hello world" program, `./x.py test
> --no-run`, or equivalent "smoke tests". In particular, this requirement may
> apply if the target builds host tools, or if the tests in question provide
> substantial value via early detection of critical problems.
There are no no-std tests in the tree that I'm aware of.
> - Building the target in CI must not take substantially longer than the current
> slowest target in CI, and should not substantially raise the maintenance
> burden of the CI infrastructure. This requirement is subjective, to be
> evaluated by the infrastructure team, and will take the community importance
> of the target into account.
Building libcore is quite fast.
> - Tier 2 targets should, if at all possible, support cross-compiling. Tier 2
> targets should not require using the target as the host for builds, even if
> the target supports host tools.
It does.
> - In addition to the legal requirements for all targets (specified in the tier
> 3 requirements), because a tier 2 target typically involves the Rust project
> building and supplying various compiled binaries, incorporating the target
> and redistributing any resulting compiled binaries (e.g. built libraries,
> host tools if any) must not impose any onerous license requirements on any
> members of the Rust project, including infrastructure team members and those
> operating CI systems. This is a subjective requirement, to be evaluated by
> the approving teams.
Just libcore required (and liballoc). No known issues here.
> - Tier 2 targets must not impose burden on the authors of pull requests, or
> other developers in the community, to ensure that tests pass for the target.
Noted
> - The target maintainers should regularly run the testsuite for the target
The https://github.com/rust-embedded/cortex-ar repository will be changed to use the rustup component when available.
> and should fix any test failures in a reasonably timely fashion.
Noted
Promote armv8r-none-eabihf target to Tier 2
This PR promotes armv8r-none-eabihf to Tier 2, joining armv7r-none-eabi, armv7r-none-eabihf and armv7a-none-eabi.
This PR wil be rebased once https://github.com/rust-lang/rust/pull/146419 completes the queue.
> - A tier 2 target must have value to people other than its maintainers. (It may
> still be a niche target, but it must not be exclusively useful for an
> inherently closed group.)
The `armv8r-none-eabihf` target is for the Arm Cortex-R52 processor, as found in a number of Automotive SoCs that have just been released, or are about to be released. Currently SoCs are available from NXP and Renesas.
>- A tier 2 target must have a designated team of developers (the "target
> maintainers") available to consult on target-specific build-breaking issues,
> or if necessary to develop target-specific language or library implementation
> details. This team must have at least 2 developers.
The Embedded Devices Working Group's Arm Team have just started maintaining this target.
> - The target must not place undue burden on Rust developers not specifically
> concerned with that target. Rust developers are expected to not gratuitously
> break a tier 2 target, but are not expected to become experts in every tier 2
> target, and are not expected to provide target-specific implementations for
> every tier 2 target.
This target is highly similar to a number of existing Tier 2 targets, including `armv7r-none-eabihf` and so it should not add undue burden.
> - The target must provide documentation for the Rust community explaining how
> to build for the target using cross-compilation, and explaining how to run
> tests for the target. If at all possible, this documentation should show how
> to run Rust programs and tests for the target using emulation, to allow
> anyone to do so. If the target cannot be feasibly emulated, the documentation
> should explain how to obtain and work with physical hardware, cloud systems,
> or equivalent.
https://doc.rust-lang.org/nightly/rustc/platform-support/armv8r-none-eabihf.html exists and was updated in https://github.com/rust-lang/rust/pull/146419/
> - The target must document its baseline expectations for the features or
> versions of CPUs, operating systems, libraries, runtime environments, and
> similar.
I believe it does.
> - If introducing a new tier 2 or higher target that is identical to an existing
> Rust target except for the baseline expectations for the features or versions
> of CPUs, operating systems, libraries, runtime environments, and similar,
> then the proposed target must document to the satisfaction of the approving
> teams why the specific difference in baseline expectations provides
> sufficient value to justify a separate target.
The Armv8-R architecture introduces a new FPU type, the fp-armv8, and so this requires a unique target.
> - Tier 2 targets must not leave any significant portions of `core` or the
> standard library unimplemented or stubbed out, unless they cannot possibly be
> supported on the target.
It has a full libcore, as per the other arm*-none-* targets.
> - The code generation backend for the target should not have deficiencies that
> invalidate Rust safety properties, as evaluated by the Rust compiler team.
It should be the same backend as `armv7r-none-eabihf` and friends, except for FPU support, which is already covered in `thumbv8m.main-none-eabihf`. There are no issues that I know of.
> - If the target supports C code, and the target has an interoperable calling
> convention for C code, the Rust target must support that C calling convention
> for the platform via `extern "C"`. The C calling convention does not need to
> be the default Rust calling convention for the target, however.
The ABI is EABI, the same as many other Arm targets.
> - The target must build reliably in CI, for all components that Rust's CI
> considers mandatory.
The https://github.com/rust-embedded/cortex-ar repository regularly builds this target with `-Zbuild-std=core` and it seems fine.
> - The approving teams may additionally require that a subset of tests pass in
> CI, such as enough to build a functional "hello world" program, `./x.py test
> --no-run`, or equivalent "smoke tests". In particular, this requirement may
> apply if the target builds host tools, or if the tests in question provide
> substantial value via early detection of critical problems.
There are no no-std tests in the tree that I'm aware of.
> - Building the target in CI must not take substantially longer than the current
> slowest target in CI, and should not substantially raise the maintenance
> burden of the CI infrastructure. This requirement is subjective, to be
> evaluated by the infrastructure team, and will take the community importance
> of the target into account.
Building libcore is quite fast.
> - Tier 2 targets should, if at all possible, support cross-compiling. Tier 2
> targets should not require using the target as the host for builds, even if
> the target supports host tools.
It does.
> - In addition to the legal requirements for all targets (specified in the tier
> 3 requirements), because a tier 2 target typically involves the Rust project
> building and supplying various compiled binaries, incorporating the target
> and redistributing any resulting compiled binaries (e.g. built libraries,
> host tools if any) must not impose any onerous license requirements on any
> members of the Rust project, including infrastructure team members and those
> operating CI systems. This is a subjective requirement, to be evaluated by
> the approving teams.
Just libcore required (and liballoc). No known issues here.
> - Tier 2 targets must not impose burden on the authors of pull requests, or
> other developers in the community, to ensure that tests pass for the target.
Noted
> - The target maintainers should regularly run the testsuite for the target
The https://github.com/rust-embedded/cortex-ar repository will be changed to use the rustup component when available.
> and should fix any test failures in a reasonably timely fashion.
Noted
Set the minimum deployment target for `aarch64-apple-watchos`
To match what's done in LLVM 21 and Xcode 26, watchOS 26 is the first OS version that actually runs true Aarch64 binaries. This affects the object files we create, and the linker invocation when using `-Clinker=ld`.
See also investigation in https://github.com/rust-lang/rust/issues/147223.
Add a new `wasm32-wasip3` target to Rust
This commit adds a new tier 3 target to rustc, `wasm32-wasip3`. This follows in the footsteps of the previous `wasm32-wasip2` target and is used to represent binding to the WASIp3 set of APIs managed by the WASI subgroup to the WebAssembly Community Group.
As of now the WASIp3 set of APIs are not finalized nor standardized. They're in the process of doing so and the current trajectory is to have the APIs published in December of this year. The goal here is to get the wheels turning in Rust to have the target in a
more-ready-than-nonexistent state by the time this happens in December.
For now the `wasm32-wasip3` target looks exactly the same as `wasm32-wasip2` except that `target_env = "p3"` is specified. This indicates to crates in the ecosystem that WASIp3 APIs should be used, such as the [`wasip3` crate]. Over time this target will evolve as implementation in guest toolchains progress, notably:
* The standard library will use WASIp3 APIs natively once they're finalized in the WASI subgroup.
* Support through `wasi-libc` will be updated to use WASIp3 natively which Rust will then transitively use.
* Longer-term, features such as cooperative multithreading will be added to the WASIp3-track of targets to enable using `std::thread`, for example, on this target.
These changes are all expected to be non-breaking changes for users of this target. Runtimes supporting WASIp3, currently Wasmtime and Jco, support WASIp2 APIs as well and will work with components whether or not they import WASIp2, both WASIp2 and WASIp3, or just WASIp3 APIs. This means that changing the internal implementation details of libstd over time is expected to be a non-breaking change.
[`wasip3` crate]: https://crates.io/crates/wasip3
