Jacob Bramley
4364634d74
Remove some trailing whitespace.
2023-01-09 15:08:12 +00:00
Jacob Bramley
665e33f3be
Match Neon test features to their intrinsics.
...
The tests can run if and only if the target_features for the
corresponding intrinsics are detected at run-time, so make sure that the
tests have an appropriate `simd_test()`.
This fixes some failures due to tests running when they shouldn't. For
example, some tests would fail on hardware that lacks "fcma".
2023-01-09 15:08:12 +00:00
Jacob Bramley
f966d451b5
Decouple TargetFeature strings.
...
"arm" and "aarch64" support different sets of `target_feature` and
`simd_test` arguments, and for "arm", the set of features that can be
dynamically detected is different again. Restructure the generator code
to allow this to be expressed accurately (in future patches).
This implementation preserves the way that target features are specified
for shared intrinsics, because this has an impact on the generated
documentation. In particular, rustdoc cannot look inside
`cfg_attr(target_arch = ...)` tests, so we use unconditional
`target_feature` attributes where possible.
2023-01-09 15:08:12 +00:00
Nugine
284e7768c9
Resolve old FIXME comments ( #1364 )
2023-01-06 11:52:12 +00:00
Nugine
ee060659d9
Stabilize cmpxchg16b instrinsic ( #1358 )
...
Resolves https://github.com/rust-lang/stdarch/issues/827
2023-01-05 17:52:56 +00:00
Ruben De Smet
755a95168f
Move vector combine intrisics to arm/neon.rs ( #1363 )
2022-12-11 18:09:13 +00:00
Amanieu d'Antras
f6f1ec11fa
Fix typo in LLVM intrinsic names ( #1362 )
...
Fixes https://github.com/rust-lang/stdarch/issues/1361
2022-11-28 03:11:45 +00:00
Caleb Zulawski
0b2b195544
Rename misleading features ( #1355 )
2022-11-21 20:56:45 +00:00
Nugine
128cb1c6a7
Use simd intrinsics for max and min ( #1357 )
2022-11-21 20:55:44 +00:00
Nugine
83cd38d056
Fix undefined behavior in movemask_epi8 ( #1354 )
...
Fixes https://github.com/rust-lang/stdarch/issues/1347
2022-11-16 18:15:48 +00:00
Amanieu d'Antras
75127705cc
Remove workaround for old LLVM issue ( #1353 )
...
Fixes https://github.com/rust-lang/stdarch/issues/794
2022-11-16 15:57:12 +00:00
Amanieu d'Antras
c80d9794e0
Don't require AVX512 for 128/256-bit GFNI & VPCLMULQDQ intrinsics ( #1349 )
2022-10-30 01:56:06 +01:00
Amanieu d'Antras
55f9fcda26
Don't require AVX512 for 256-bit VAES intrinsics ( #1348 )
2022-10-27 19:51:16 +01:00
Amanieu d'Antras
eea72e2ed7
Mark arm_shared intrinsics as stable on all target except ARM ( #1345 )
2022-10-25 20:18:19 +01:00
Amanieu d'Antras
9707fba048
Fix undefined behavior in SSE4.2 test ( #1341 )
2022-10-25 20:18:02 +01:00
Yuri Astrakhan
81c221f058
Edition 2021, apply clippy::uninlined_format_args fix ( #1339 )
2022-10-25 20:17:23 +01:00
Rageking8
90f618d8dd
Fix dupe word typos ( #1344 )
2022-10-25 15:01:34 +01:00
Chris Wailes
13d20910b7
Update the Android Docker files to Ubuntu 22.04 ( #1338 )
2022-10-04 09:19:36 +01:00
Jacob Bramley
8a944e5a5f
Add HWCAP2 support for AArch64 Linux. ( #1335 )
2022-09-22 05:31:46 +01:00
luojia65
e0e9e96c1d
crate: use target feature v1.1
2022-09-13 05:03:04 +02:00
luojia65
a49ca40768
riscv: P extension intrinsics for packed SIMD (part 1)
...
Implement by inline assembly for now, uses `pure, nomem, nostack` for
all packed simd arithmetic instructions. Uses `inlateout` when it
requires using the same register for input and output, use `lateout`
for all output registers.
This commit also includes a rearrangement of shared risc-v architecture
module to improve documents. It also includes a doc test fix, gate sm3/4
and use explict sm3/4 instruction under rustc target feature.
2022-09-13 05:03:04 +02:00
Tobias Bengtsson
ee67399527
Fix documentation of __m256bh and __m512bh structs
2022-09-12 22:20:43 +02:00
Artyom Pavlov
23ec6d7dd0
Use mov and xchg instead of movl(q) and xchgl(q)
2022-09-08 13:08:39 +02:00
Artyom Pavlov
ef7ae083b7
Remove late specifiers in __cpuid_count
2022-09-08 13:08:39 +02:00
bjorn3
fc51fc4da4
Remove simd_shuffle<n> usage in favor of simd_shuffle
...
This slightly reduces the amount of intrinsics codegen backends need to implement.
2022-09-06 03:36:27 +02:00
bjorn3
1536639d42
Use simd_bitmask intrinsic in a couple of places
2022-09-05 23:38:14 +02:00
Tomasz Miąsko
64e9268deb
Fix links in documentation of cmpxchg16b
2022-08-23 15:51:52 +02:00
Amanieu d'Antras
e79701c56e
Properly fix vext intrinsic tests
...
This was previously done as part of #1326 , but it modified generated
code without fixing the root issue in neon.spec.
2022-08-22 23:46:15 +02:00
Maybe Waffle
1a2eac5986
Replace some calls to pointer::offset with add and sub
2022-08-22 22:41:21 +02:00
Amanieu d'Antras
82cb569895
Tweak constant for ARM vext instruction tests
2022-08-20 22:18:54 +02:00
Amanieu d'Antras
53d56091c6
Use llvm.ppc.altivec.lvx intrinsic for vec_ld
...
The `vec_ld` intrinsic is expected to automatically round the given
address down to a 16-byte boundary.
2022-08-20 22:18:54 +02:00
psvri
8119ecd492
Adding doc links for arm neon intrinsics
2022-08-12 19:51:56 +02:00
psvri
40668050cf
Adding doc links for arm crypto and aes intrinsics
2022-08-12 17:27:12 +02:00
Amanieu d'Antras
c01441b696
Remove instruction tests for __mmask* intrinsics
...
We generate normal scalar code for these, not specific intructions.
2022-08-12 17:26:16 +02:00
Palladium
bdfd56734d
Adding documentation links for arm crc32 intrinsics ( #1316 )
2022-08-09 20:56:09 +01:00
tmiasko
c7eadc8f06
Remove restrictions on compare-exchange memory ordering. ( #1315 )
2022-07-18 11:51:36 +01:00
Usamoi
1154adb436
Fix a typo in the document. ( #1314 )
2022-07-17 13:58:10 +01:00
tmiasko
b186197c7c
Update atomic intrinsics ( #1313 )
2022-07-02 00:53:50 +01:00
Thom Chiovoloni
3845dea2a6
Ensure the neon vector aggregates like float32x4x4_t are #[repr(C)] ( #1309 )
2022-06-13 14:40:01 +01:00
Urgau
e4d28b2c5c
Remove useless conditional compilation ( #1308 )
2022-06-10 00:14:17 +01:00
Simon Schubert
a390bd340b
Fix ARM vbsl* NEON intrinsics ( #1191 ) ( #1307 )
2022-05-16 22:44:28 +01:00
est31
6a28c9ca8b
Allow unused macro arms for simd_shuffle16 too
2022-05-10 19:15:00 +02:00
est31
cf471eb26e
Allow unused macro rules for two macros ( #1305 )
2022-05-10 00:48:31 +01:00
Sam Parker
f6cf8d45b0
Wasm simd128 pairwise/lane-wise ( #1302 )
2022-04-29 14:11:39 +01:00
Matan Hamilis
f4d6903728
Typo in _mm_xor_pd description ( #1304 )
2022-04-29 01:30:11 +01:00
Jamie Cunliffe
e75d75e292
Add the rdm target feature to the sqrdmlsh intrinsic. ( #1285 )
2022-04-08 19:29:11 +01:00
Jacob Pratt
64f4469b23
Remove use of #[rustc_deprecated]
2022-04-08 14:04:36 +02:00
Ben Kimock
f2bfba1a11
Remove feature gates for stabilized features
2022-03-28 08:20:15 +02:00
Ben Kimock
945ccb4c3f
Change remaining _undefined_ functions to zero-init
2022-03-28 08:20:15 +02:00
Alex Touchet
626654b486
Use SPDX license format and update packed_simd crate link ( #1297 )
2022-03-17 10:55:51 +00:00
