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992 Commits

Author SHA1 Message Date
Артём Павлов
0301eced58 Update Intel Intrinsics Guide links 2023-02-18 20:34:16 +01:00
bwmf2
1c18225f32 Fix typo 2023-02-18 20:02:17 +01:00
Taiki Endo
e6b7951ccd std_detect: Remove extra cfg 
This module is already `#[cfg(target_arch = "aarch64")]`.
 2023-02-13 02:04:54 +01:00
Taiki Endo
2ebd1395ec std_detect: Only check features that are known to be available on armv8.0 cores if CPU is Exynos 9810 2023-02-13 02:04:54 +01:00
Taiki Endo
e9d18c6b18 std_detect: Workaround Exynos 9810 bug on aarch64 Android 
Samsung Exynos 9810 has a bug that big and little cores have different
ISAs. And on older Android (pre-9), the kernel incorrectly reports
that features available only on some cores are available on all cores.

https://reviews.llvm.org/D114523
 2023-02-13 02:04:54 +01:00
Taiki Endo
dc49234574
std_detect: Support run-time detection of FEAT_LSE2 on aarch64 BSD (#1379) 2023-02-11 17:31:21 +00:00
Taiki Endo
57c492180d
std_detect: Update platform support docs (#1380) 2023-02-11 16:10:11 +00:00
Felix
217a7d106a
update the URL of Intel CPUID reference book (#1376) 2023-02-07 15:17:59 +01:00
Taiki Endo
1829ee06f0
std_detect: Always avoid dlsym on *-linux-gnu* targets (#1375) 2023-02-03 18:23:09 +00:00
Taiki Endo
a36f5bd7c8 std_detect: Support run-time detection on aarch64 OpenBSD 2023-01-26 23:33:52 +00:00
Taiki Endo
d3bb923c82 std_detect: Split os/aarch64.rs' detect_features into reading and parsing 2023-01-26 23:33:52 +00:00
Taiki Endo
674fd58f60 std_detect: Move aarch64 freebsd test to tests/cpu-detection.rs 2023-01-26 23:33:52 +00:00
Taiki Endo
e706a13add std_detect: Add test for feature detection on aarch64 Windows 2023-01-23 22:26:08 +00:00
Taiki Endo
505d4e8d48 std_detect: Support detecting lse/dotprod/jsconv/rcpc on aarch64 Windows 2023-01-23 22:26:08 +00:00
Jacob Bramley
6e5b949ee7 Check and pass the ACLE licence on to generated tests. 
The generated tests are transient, and aren't committed, so this is
primarily a safety check.
 2023-01-23 18:58:28 +00:00
Jacob Bramley
4407146bb8 Declare licence for crates/intrinsics-test. 2023-01-23 18:58:28 +00:00
Urgau
8048734108 Remove obsolete cfg for nvptx 
Following to the compiler MCP 496
(https://github.com/rust-lang/compiler-team/issues/496)
 2023-01-22 18:20:30 +00:00
Jacob Bramley
262d7c77bf Don't declare f16c_target_feature. 
f16c_target_feature was recently stabilised.

This fixes a warning that results in a CI failure (due to `-D
stable-features`) with current nightly Rust.
 2023-01-22 15:38:02 +00:00
Ralf Jung
5afa869e0a use inline const for last simd_shuffle argument 2023-01-10 00:23:14 +00:00
Jacob Bramley
4364634d74 Remove some trailing whitespace. 2023-01-09 15:08:12 +00:00
Jacob Bramley
665e33f3be Match Neon test features to their intrinsics. 
The tests can run if and only if the target_features for the
corresponding intrinsics are detected at run-time, so make sure that the
tests have an appropriate `simd_test()`.

This fixes some failures due to tests running when they shouldn't. For
example, some tests would fail on hardware that lacks "fcma".
 2023-01-09 15:08:12 +00:00
Jacob Bramley
f966d451b5 Decouple TargetFeature strings. 
"arm" and "aarch64" support different sets of `target_feature` and
`simd_test` arguments, and for "arm", the set of features that can be
dynamically detected is different again. Restructure the generator code
to allow this to be expressed accurately (in future patches).

This implementation preserves the way that target features are specified
for shared intrinsics, because this has an impact on the generated
documentation. In particular, rustdoc cannot look inside
`cfg_attr(target_arch = ...)` tests, so we use unconditional
`target_feature` attributes where possible.
 2023-01-09 15:08:12 +00:00
Nugine
284e7768c9
Resolve old FIXME comments (#1364) 2023-01-06 11:52:12 +00:00
Caleb Zulawski
39c2524e1b
Detect MOVBE (#1356) 2023-01-05 17:54:07 +00:00
Nugine
ee060659d9
Stabilize cmpxchg16b instrinsic (#1358) 
Resolves https://github.com/rust-lang/stdarch/issues/827
 2023-01-05 17:52:56 +00:00
Ruben De Smet
755a95168f
Move vector combine intrisics to arm/neon.rs (#1363) 2022-12-11 18:09:13 +00:00
Amanieu d'Antras
f6f1ec11fa
Fix typo in LLVM intrinsic names (#1362) 
Fixes https://github.com/rust-lang/stdarch/issues/1361
 2022-11-28 03:11:45 +00:00
Caleb Zulawski
0b2b195544
Rename misleading features (#1355) 2022-11-21 20:56:45 +00:00
Nugine
128cb1c6a7
Use simd intrinsics for max and min (#1357) 2022-11-21 20:55:44 +00:00
Nugine
83cd38d056
Fix undefined behavior in movemask_epi8 (#1354) 
Fixes https://github.com/rust-lang/stdarch/issues/1347
 2022-11-16 18:15:48 +00:00
Amanieu d'Antras
75127705cc
Remove workaround for old LLVM issue (#1353) 
Fixes https://github.com/rust-lang/stdarch/issues/794
 2022-11-16 15:57:12 +00:00
gendx
45e3039ee9
Detect CPU features with Linux methods on Android for non-Intel CPUs. (#1351) 
Co-authored-by: Amanieu d'Antras <amanieu@gmail.com>
 2022-11-09 18:38:48 +00:00
Mateusz Mikuła
9f7ded4282
Fix line endings to use LF (#1350) 2022-11-09 00:37:10 +00:00
Amanieu d'Antras
c80d9794e0
Don't require AVX512 for 128/256-bit GFNI & VPCLMULQDQ intrinsics (#1349) 2022-10-30 01:56:06 +01:00
Amanieu d'Antras
55f9fcda26
Don't require AVX512 for 256-bit VAES intrinsics (#1348) 2022-10-27 19:51:16 +01:00
Amanieu d'Antras
eea72e2ed7
Mark arm_shared intrinsics as stable on all target except ARM (#1345) 2022-10-25 20:18:19 +01:00
Amanieu d'Antras
9707fba048
Fix undefined behavior in SSE4.2 test (#1341) 2022-10-25 20:18:02 +01:00
Yuri Astrakhan
81c221f058
Edition 2021, apply clippy::uninlined_format_args fix (#1339) 2022-10-25 20:17:23 +01:00
Rageking8
90f618d8dd
Fix dupe word typos (#1344) 2022-10-25 15:01:34 +01:00
Chris Wailes
13d20910b7
Update the Android Docker files to Ubuntu 22.04 (#1338) 2022-10-04 09:19:36 +01:00
Jacob Bramley
8a944e5a5f
Add HWCAP2 support for AArch64 Linux. (#1335) 2022-09-22 05:31:46 +01:00
luojia65
e0e9e96c1d crate: use target feature v1.1 2022-09-13 05:03:04 +02:00
luojia65
a49ca40768 riscv: P extension intrinsics for packed SIMD (part 1) 
Implement by inline assembly for now, uses `pure, nomem, nostack` for
all packed simd arithmetic instructions. Uses `inlateout` when it
requires using the same register for input and output, use `lateout`
for all output registers.

This commit also includes a rearrangement of shared risc-v architecture
module to improve documents. It also includes a doc test fix, gate sm3/4
and use explict sm3/4 instruction under rustc target feature.
 2022-09-13 05:03:04 +02:00
Tobias Bengtsson
ee67399527 Fix documentation of __m256bh and __m512bh structs 2022-09-12 22:20:43 +02:00
Charles Lew
676d095f0a Bump cfg-if dependency to 1.0 2022-09-11 13:05:05 +02:00
Artyom Pavlov
23ec6d7dd0 Use mov and xchg instead of movl(q) and xchgl(q) 2022-09-08 13:08:39 +02:00
Artyom Pavlov
ef7ae083b7 Remove late specifiers in __cpuid_count 2022-09-08 13:08:39 +02:00
bjorn3
fc51fc4da4 Remove simd_shuffle<n> usage in favor of simd_shuffle 
This slightly reduces the amount of intrinsics codegen backends need to implement.
 2022-09-06 03:36:27 +02:00
bjorn3
1536639d42 Use simd_bitmask intrinsic in a couple of places 2022-09-05 23:38:14 +02:00
Tomasz Miąsko
64e9268deb Fix links in documentation of cmpxchg16b 2022-08-23 15:51:52 +02:00