luojia65
e0e9e96c1d
crate: use target feature v1.1
2022-09-13 05:03:04 +02:00
luojia65
a49ca40768
riscv: P extension intrinsics for packed SIMD (part 1)
...
Implement by inline assembly for now, uses `pure, nomem, nostack` for
all packed simd arithmetic instructions. Uses `inlateout` when it
requires using the same register for input and output, use `lateout`
for all output registers.
This commit also includes a rearrangement of shared risc-v architecture
module to improve documents. It also includes a doc test fix, gate sm3/4
and use explict sm3/4 instruction under rustc target feature.
2022-09-13 05:03:04 +02:00
Tobias Bengtsson
ee67399527
Fix documentation of __m256bh and __m512bh structs
2022-09-12 22:20:43 +02:00
Charles Lew
676d095f0a
Bump cfg-if dependency to 1.0
2022-09-11 13:05:05 +02:00
Artyom Pavlov
23ec6d7dd0
Use mov and xchg instead of movl(q) and xchgl(q)
2022-09-08 13:08:39 +02:00
Artyom Pavlov
ef7ae083b7
Remove late specifiers in __cpuid_count
2022-09-08 13:08:39 +02:00
bjorn3
fc51fc4da4
Remove simd_shuffle<n> usage in favor of simd_shuffle
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This slightly reduces the amount of intrinsics codegen backends need to implement.
2022-09-06 03:36:27 +02:00
bjorn3
1536639d42
Use simd_bitmask intrinsic in a couple of places
2022-09-05 23:38:14 +02:00
Tomasz Miąsko
64e9268deb
Fix links in documentation of cmpxchg16b
2022-08-23 15:51:52 +02:00
James McGregor
893bbdd717
Use load intrinsic and loop for intrinsic-test programs. Add --release flag back to intrinsic-test programs.
2022-08-22 23:46:30 +02:00
Amanieu d'Antras
e79701c56e
Properly fix vext intrinsic tests
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This was previously done as part of #1326 , but it modified generated
code without fixing the root issue in neon.spec.
2022-08-22 23:46:15 +02:00
Maybe Waffle
1a2eac5986
Replace some calls to pointer::offset with add and sub
2022-08-22 22:41:21 +02:00
Tomasz Miąsko
39f73ac0b3
Allow internal use of stdsimd from detect_feature
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This allows using feature detection macros, without placing a
requirement of enabled stdsimd feature gate from end users.
A follow-up to changes from #1311 , which introduced the new macro.
2022-08-22 22:40:39 +02:00
Waffle Maybe
86061fc080
fix target name in contributing.md
2022-08-20 22:19:34 +02:00
Amanieu d'Antras
82cb569895
Tweak constant for ARM vext instruction tests
2022-08-20 22:18:54 +02:00
Amanieu d'Antras
53d56091c6
Use llvm.ppc.altivec.lvx intrinsic for vec_ld
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The `vec_ld` intrinsic is expected to automatically round the given
address down to a 16-byte boundary.
2022-08-20 22:18:54 +02:00
psvri
8119ecd492
Adding doc links for arm neon intrinsics
2022-08-12 19:51:56 +02:00
psvri
40668050cf
Adding doc links for arm crypto and aes intrinsics
2022-08-12 17:27:12 +02:00
Amanieu d'Antras
c01441b696
Remove instruction tests for __mmask* intrinsics
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We generate normal scalar code for these, not specific intructions.
2022-08-12 17:26:16 +02:00
Amanieu d'Antras
7850f6e701
Update ubuntu 21.10 docker containers to 22.04
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Ubuntu 22.10 is EOL.
2022-08-12 17:26:16 +02:00
Palladium
bdfd56734d
Adding documentation links for arm crc32 intrinsics ( #1316 )
2022-08-09 20:56:09 +01:00
tmiasko
c7eadc8f06
Remove restrictions on compare-exchange memory ordering. ( #1315 )
2022-07-18 11:51:36 +01:00
Usamoi
1154adb436
Fix a typo in the document. ( #1314 )
2022-07-17 13:58:10 +01:00
Adam Gemmell
ba9ca43154
Allow mapping a runtime feature to a set of target_features ( #1311 )
2022-07-02 00:55:03 +01:00
tmiasko
b186197c7c
Update atomic intrinsics ( #1313 )
2022-07-02 00:53:50 +01:00
Adam Gemmell
0798ac34c7
Fully qualify recursive macro calls ( #1310 )
2022-06-21 00:20:12 +01:00
Thom Chiovoloni
3845dea2a6
Ensure the neon vector aggregates like float32x4x4_t are #[repr(C)] ( #1309 )
2022-06-13 14:40:01 +01:00
Urgau
e4d28b2c5c
Remove useless conditional compilation ( #1308 )
2022-06-10 00:14:17 +01:00
Simon Schubert
a390bd340b
Fix ARM vbsl* NEON intrinsics ( #1191 ) ( #1307 )
2022-05-16 22:44:28 +01:00
est31
6a28c9ca8b
Allow unused macro arms for simd_shuffle16 too
2022-05-10 19:15:00 +02:00
est31
cf471eb26e
Allow unused macro rules for two macros ( #1305 )
2022-05-10 00:48:31 +01:00
Sam Parker
f6cf8d45b0
Wasm simd128 pairwise/lane-wise ( #1302 )
2022-04-29 14:11:39 +01:00
Jane Lusby
bae054af11
Add stdsimd feature to allow_internal_unstable attribute in feature detect macros ( #1303 )
2022-04-29 01:30:25 +01:00
Matan Hamilis
f4d6903728
Typo in _mm_xor_pd description ( #1304 )
2022-04-29 01:30:11 +01:00
Jamie Cunliffe
e75d75e292
Add the rdm target feature to the sqrdmlsh intrinsic. ( #1285 )
2022-04-08 19:29:11 +01:00
Jacob Pratt
64f4469b23
Remove use of #[rustc_deprecated]
2022-04-08 14:04:36 +02:00
Ben Kimock
f2bfba1a11
Remove feature gates for stabilized features
2022-03-28 08:20:15 +02:00
Ben Kimock
945ccb4c3f
Change remaining _undefined_ functions to zero-init
2022-03-28 08:20:15 +02:00
Alex Touchet
626654b486
Use SPDX license format and update packed_simd crate link ( #1297 )
2022-03-17 10:55:51 +00:00
relrelb
528c020edf
Fix broken links ( #1294 )
2022-03-16 14:51:45 +00:00
Luca Barbato
d3f6f21a26
Import the asm macro in std_detect ( #1290 )
2022-03-11 17:12:29 +00:00
Guillaume Gomez
b51baab99c
Replace unused doc comment with code comment ( #1286 )
2022-03-02 17:24:38 +00:00
Amanieu d'Antras
b25548658a
Updates for LLVM 14 on nightly
2022-02-19 20:44:04 +00:00
Amanieu d'Antras
831dd7190d
Stabilize vget_low_s8 on AArch64
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This was missed when most of the AArch64 intrinsics were stabilized.
2022-02-19 20:44:04 +00:00
Amanieu d'Antras
bf3a73b3e8
Avoid the use of #[cfg(doc)] in std_detect ( #1283 )
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Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
2022-02-17 12:49:50 +00:00
Adam Gemmell
3362d525c5
Split aarch64 pauth feature into paca and pacg ( #1259 )
2022-02-10 14:59:40 +00:00
Adam Gemmell
c52d7f5b66
Stabilise is_aarch64_feature_detected! under simd_aarch64 feature ( #1239 )
2022-02-09 19:33:25 +00:00
minybot
3f075854cc
Add AVX512F expandloadu ( #1280 )
2022-02-08 15:09:09 +00:00
minybot
6679b4a6d4
Complete avx512vbmi2 ( #1279 )
2022-02-06 13:27:31 +00:00
Luo Jia
0888677e5c
riscv: K extension (part 1), floating-point control and state register ( #1278 )
2022-02-06 13:23:25 +00:00
