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1060 Commits

Author SHA1 Message Date
Gijs Burghoorn
8a23f93e8b Fix: #1464 for rv64 zk 2023-09-22 10:08:56 +08:00
Eduardo Sánchez Muñoz
bc7c676407 Format 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
4551a9acab Improve _mm_max_ps, _mm_min_pd, _mm_max_pd tests 
Includes cases to test -0.0, like done for `_mm_min_ps`.
 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
26425131b6 Improve SSE2 slli/srli/srai tests 
Includes cases where the shift amount is equal to the number of bits
 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
bb0d9a41e1 Improve SSE2 sll/srl/sra tests 
Includes cases where the shift amount is equal or greater to the number of bits.
 2023-09-22 10:07:29 +08:00
Eduardo Sánchez Muñoz
f056604ac2 Add #[track_caller] to assert_eq_* functions 2023-09-22 10:07:29 +08:00
Gijs Burghoorn
c460cf6706 Impl: Add RISC-V Zb intrinsics 2023-09-01 18:32:40 +02:00
Gijs Burghoorn
4be26a9497 Fix: Remove assert_instr for RISCV, see #1464 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
f669624b6f Fix: Add constant for assert_instr 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
0b5a5ce567 Fix: Remove unused arch::asm imports 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
cf14e15b7f Impr: Remove pack instructions as instrinsics 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
164af4a836 Chore: Cargo format 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
0e0a78a3f0 Fix: Utilize LLVM intrinsics where possible 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
7fd998870d Fix: Change to 'rustc_legacy_const_generics' 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
992bd5e1a9 Fix: Assembly mistakes in RISC-V Zk extensions 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
1c5eb32416 Chore cargo fmt 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
f0be271de9 Implement RISC-V Zk extension intrinsics 2023-08-31 23:12:32 +02:00
Gijs Burghoorn
e301d8bba4 Depend on riscv_ext_intrinsics feature. 2023-08-31 23:12:32 +02:00
Eduardo Sánchez Muñoz
877098179a Fix _mm_srli_epi64 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
7f5b70be72 Implement AVX512BW 16-bit shift by immediate (srai_epi16) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
427bb149f0 Implement AVX512BW 16-bit shift by immediate (srli_epi16) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
0c0f72ee7f Implement AVX512BW 16-bit shift by immediate (slli_epi16) with simd_shl instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
4b2efda9a9 Implement AVX512F 64-bit shift by immediate (srai_epi64) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
01ff55e216 Implement AVX512F 32-bit shift by immediate (srai_epi32) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
29ba594589 Implement AVX512F 64-bit shift by immediate (srli_epi64) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
c3fdf91585 Implement AVX512F 32-bit shift by immediate (srli_epi32) with simd_shr instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
25a978a69f Implement AVX512F 64-bit shift by immediate (slli_epi64) with simd_shl instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
bf3a28f6ad Implement AVX512F 32-bit shift by immediate (slli_epi32) with simd_shl instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
f942d69471 Implement AVX2 shift by immediate (slli, srli, srai) with simd_sh{l,r} instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
819fe11c49 Implement SSE2 shift by immediate (slli, srli, srai) with simd_sh{l,r} instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Eduardo Sánchez Muñoz
3b7dc00f66 Implement SSE2 and AVX unaligned stores (storeu) with <*mut T>::write_unaligned instead of LLVM intrinsics 2023-08-30 23:38:21 +02:00
Amanieu d'Antras
17daea9747 Update instruction tests for LLVM 17 2023-08-29 15:21:34 +02:00
Amanieu d'Antras
fff032b929 Fix CI on wasm32-wasi 
The cc dependency doesn't compile on wasi, so only include it for
windows targets.
 2023-08-29 15:21:34 +02:00
Amanieu d'Antras
5161de5da4 Add #![allow(internal_unstable)] 
This is required to avoid build failures when using rustc features
intended only for use by the standard library.
 2023-08-29 15:21:34 +02:00
zica
9a991c7a67 Fix typo 2023-08-13 10:55:01 +02:00
Bruce Mitchener
b781d20dc8 clippy: unnecessary cast warnings on x86. 
The full warning is "casting raw pointers to the same type and constness
is unnecessary"
 2023-08-04 00:06:36 +01:00
Bruce Mitchener
02b324c46a clippy: Some simple clippy fixes. 2023-07-30 10:58:50 +01:00
Bruce Mitchener
87276b002c Use #[rustfmt::skip] instead of #[cfg_attr(...)]. 2023-07-30 10:58:20 +01:00
Bruce Mitchener
5c4a950591 docs: Fix warnings and typos. 
* Fix typo in HTML tag
* Mark some things with backticks to fix warnings about
  unescaped square brackets.
* Spell "initialize" correctly to fix typos.
 2023-07-30 10:57:20 +01:00
Amanieu d'Antras
08e8e220fc Remove redundant definitions 
Fixes #1446
 2023-07-30 08:00:01 +01:00
Amanieu d'Antras
94867fad87 Remove #[target_feature] from const fn 2023-07-29 22:38:57 +01:00
Luca Barbato
9eddada872 Add vec_xl 2023-07-03 20:39:57 +01:00
Luca Barbato
d834f538b4 Add vec_loge 2023-07-03 20:39:57 +01:00
Luca Barbato
34e8658bae Add vec_mfvscr 2023-07-03 20:39:57 +01:00
Luca Barbato
3bdfa0f20e Fix the documentation of vec_ceil 2023-07-03 20:39:57 +01:00
Amanieu d'Antras
cf728faa26 Fix some NEON intrinsics not appearing in standard library docs 
This happens because the docs are built for x86_64, see #1345.

Fixes #1444
 2023-06-28 21:19:48 +01:00
bjorn3
ecc8d7ccb6 Use const {} for the immediate args of _mm*_cmp_* 
Rustc_codegen_cranelift requires immediates to already be constant in
MIR unlike LLVM which only needs them constant after optimizations.
 2023-06-23 14:57:54 +02:00
Jacob Bramley
31e17e39c2 Add AArch64 vrnd*_f64 Neon intrinsics. 
The LLVM intrinsic doesn't support float64x1_t, but the required
instruction is a scalar form (e.g. `frint32x <Dd>, <Dn>`), so we can
implement these using the scalar intrinsic.

Note that Clang does not support these intrinsics, so they aren't
covered by intrinsic-test. Additional validation is included in this
patch to ensure that we're selecting an instruction with the same
behaviour as the corresponding vector form (which all have
intrinsic-tests).
 2023-06-21 18:52:21 +02:00
Jacob Bramley
0459405ea9 Add more AArch64 vrnd intrinsics. 
LLVM can't select float64x1_t variants, but float64x2_t variants work.
 2023-06-21 18:52:21 +02:00
Jacob Bramley
a9fecd8456 Support AArch32 Neon dotprod intrinsics. 
Note that the feature detection requires a recent Linux kernel (v6.2).
 2023-06-21 18:52:21 +02:00