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2,426 Commits 11 Branches 149 Tags
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1331 Commits

Author SHA1 Message Date
usamoi
a4a7184370 mark gfni, vaes, vpclmulqdq intrinsics as safe 2025-05-30 17:35:18 +00:00
Ralf Jung
9561e8e0a3 cmpxchg16b: use atomic_compare_exchange from libcore 2025-05-30 17:14:51 +00:00
Ralf Jung
b58ce625a2 allow aarch64_softfloat_neon for backwards compatibility 2025-05-21 10:39:23 +00:00
Folkert de Vries
7b995254d4 use a tuple to return the condition code 2025-05-20 16:39:24 +00:00
Folkert de Vries
42e6ad3ee8 use the right load instruction 2025-05-20 14:26:46 +00:00
Folkert de Vries
a850e8738a avx512_target_feature is now stable on nightly 2025-05-20 14:26:46 +00:00
WANG Rui
63235a6ba5 Partially stabilize LoongArch target features 2025-05-12 19:47:49 +00:00
sayantn
546e26518f Run aarch64-pc-windows-msvc runs on the new windows-11-arm runners 2025-05-06 16:10:50 +00:00
James Barford-Evans
c65583c2b3 Pr feedback for instruction & hookup CI for aarch64_be 2025-05-03 05:06:15 +00:00
James Barford-Evans
ef92b59242 fix - aarch64_be tests 2025-05-03 05:06:15 +00:00
sayantn
f8782f778b Fix errors in incorrect SAE and ROUNDING parameters 2025-05-03 05:03:31 +00:00
sayantn
ed25a9bde4 Implement sha512, sm3 and sm4 intrinsics 2025-05-01 11:30:47 +00:00
sayantn
400dab3df7 Fix stdarch-verify 2025-05-01 11:30:47 +00:00
sayantn
a21396870c Add avx512vl requirement to testsuite for avx512fp16 128 and 256 bit 2025-04-29 11:59:15 +00:00
sayantn
288ae22354 Fix errors in decoupling avx512vl and avx512dq from avx512fp16 2025-04-29 11:59:15 +00:00
sayantn
caf463ae41 Fix CI errors due to alignment issues in msvc 2025-04-29 11:59:15 +00:00
sayantn
e61df091c1 Remove workarounds for llvm/llvm-project#98306 2025-04-23 10:40:09 +00:00
Folkert de Vries
f77386cf2b run powerpc64le assert_instr on CI 2025-04-23 10:38:19 +00:00
Ralf Jung
1e3c5e3c99 use 'unadjusted' ABI for wasm LLVM intrinsics 2025-04-21 17:59:41 +00:00
sayantn
bc9e29d9be Replace cfg(stdarch_intel_sde) with STDARCH_TEST_SKIP_FUNCTION 2025-04-20 21:39:39 +00:00
sayantn
6cc17153d9 Re-enable all conditionally-disabled x86 assert_instr tests 2025-04-20 21:39:39 +00:00
bendn
3dd82b698f allow unnecessary transmutes 2025-04-17 18:27:37 +00:00
Folkert de Vries
c899659c44 add vec_extract, vec_insert, vec_promote and vec_insert_and_zero 2025-04-17 17:06:09 +00:00
sayantn
e804386587 Change void* type for gather/scatter intrinsics 2025-04-17 13:59:07 +00:00
sayantn
d6b0426127 Change void* type for cvt_storeu intrinsics 2025-04-17 13:59:07 +00:00
sayantn
376c3f33c5 Change void* type for compressstore intrinsics 2025-04-17 13:59:07 +00:00
sayantn
b10a6817d9 Change void* type for 3 intrinsics 
- `_mm512_load_si512`
 - `_mm512_loadu_si512`
 - `_mm512_stream_si512`
 2025-04-17 13:59:07 +00:00
bendn
b5046525d5 fix broken intra doc links 2025-04-11 11:30:32 +00:00
bendn
3ea2e5600f allow unnecessary transmutes 2025-03-27 21:36:07 +00:00
Folkert de Vries
9c8f736849 make documentation headers consistent 
this now always uses the name as specified by the official docs
 2025-03-26 13:50:38 +00:00
Folkert de Vries
69a7cb8be3 add s390x to the module docs 2025-03-26 13:50:38 +00:00
James Barford-Evans
2099eccb2e pr feedback - remove the commented out vcombine_f16 2025-03-25 10:53:54 +00:00
James Barford-Evans
08b9752ee1 refactor - arm_shared intrinsics are now YAML, where possible use anchor 
tags
 2025-03-25 10:53:54 +00:00
Vadim Petrochenkov
ebe8804680 sse42: Add unsafe blocks around unsafe function calls 
to fix the `unsafe_op_in_unsafe_fn` lint
 2025-03-24 23:26:29 +00:00
David Pathakjee
a083e2a6c8 Minor correction to __m512d documentation. 
A 512-bit register is f64x8, not f64x4. Likely a copy-paste error from the _m256d documentation,
which seems correct.
 2025-03-24 23:26:12 +00:00
Ralf Jung
a03fdf1441 use consistent wording around the 'undefined' intrinsics, and slightly expand their docs 2025-03-20 22:51:52 +00:00
WANG Rui
14ddd423fb Incldue loongarch64 in the list of other architectures 2025-03-20 21:54:32 +00:00
Folkert de Vries
81f6100463 move unsafe pointer writes to the surface 2025-03-16 20:02:22 +00:00
Folkert de Vries
1f202e7fe7 shink the size of type signatures 2025-03-16 20:02:22 +00:00
Folkert de Vries
3b8973d216 add vec_meadd, vec_moadd, vec_mhadd and vec_mladd 2025-03-16 20:02:22 +00:00
Folkert de Vries
44cda131be add vec_mulh 2025-03-16 20:02:22 +00:00
Folkert de Vries
f7dc654108 add vec_mulo 2025-03-16 20:02:22 +00:00
Folkert de Vries
5c61b664e7 add vec_any_* and vec_all_* 2025-03-16 20:02:22 +00:00
Folkert de Vries
e30905984c add vec_all_nan, vec_any_nan, vec_all_numeric and vec_any_numeric 2025-03-16 20:02:22 +00:00
Folkert de Vries
2667fd06ff add vec_cmpeq_idx and variations 2025-03-16 20:02:22 +00:00
Folkert de Vries
b866e43594 add vec_cmpeq and vec_cmpne 2025-03-16 20:02:22 +00:00
Folkert de Vries
8affaabfaf add vec_cmpgt, vec_cmplt, vec_cmpge, vec_cmple 2025-03-16 20:02:22 +00:00
Folkert de Vries
81a2841164 let's not use &mut until we get confirmation it's OK 2025-03-16 20:02:22 +00:00
Folkert de Vries
d218bd1624 add vec_cmprg_or_0_idx_cc and vec_cmpnrg_or_0_idx_cc 2025-03-16 20:02:22 +00:00
Folkert de Vries
790d77e4e6 add vec_cmprg_or_0_idx and vec_cmpnrg_or_0_idx 2025-03-16 20:02:22 +00:00