itsscb/rust
1
0
Fork 0
mirror of https://github.com/rust-lang/rust.git synced 2025-10-04 11:17:04 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,340 Commits 11 Branches 149 Tags
Commit Graph

62 Commits

Author SHA1 Message Date
sayantn
46fbfe9b09 Add the keylocker intrinsics 2025-02-13 10:54:53 +00:00
Eric Huss
699a872630 Update all crates to Rust 2024 2025-02-09 12:31:33 -08:00
sayantn
a635da83d7 Make assert_instr stricter 2024-12-21 10:12:32 +00:00
Yuri Astrakhan
0760ed6ca7 Minor linting 2024-09-30 13:00:24 -04:00
Mads Marquart
8a511191a0 Enable feature detection on all Apple/Darwin targets 
Tested in the simulator and on the device I had lying around, a 1st
generation iPad Mini (which isn't Aarch64, but shows that the
`sysctlbyname` calls still work even there, even if they return false).

`sysctlbyname` _should_ be safe to use without causing rejections from
the app store, as its usage is documented in:
https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics

Also, the standard library will use these soon anyhow, so this shouldn't
affect the situation:
https://github.com/rust-lang/rust/pull/129019
 2024-09-14 04:25:01 +01:00
sayantn
f22fab559e Implemented VEX versions 
Modified stdarch-test to accept VEX versions
 2024-07-06 11:00:34 +02:00
sayantn
043f3cc280 Upgraded disassembly to include windows-gnu targets 2024-06-29 19:16:48 +02:00
Amanieu d'Antras
860145884d Ignore int3 instructions when counting instructions in tests 
These are generated as padding and are not actually part of the
function.
 2024-06-07 19:18:13 +02:00
Daniel Paoliello
613efc499c Enable testing for AArch64 Windows 2024-04-19 17:21:08 +02:00
Daniel Paoliello
a00a70eacb arm64ec 2024-03-13 22:30:36 +00:00
Amanieu d'Antras
3ac4ba6670 Revert "Work around CI failures for the ARM target" 
This reverts commit 5a748ec5fabcaee29351ac3c90eee4f3e16964e7.
 2023-11-30 08:20:47 +00:00
Jacob Bramley
86cb5730ae Report missing features when skipping tests. 2023-11-30 07:48:46 +00:00
Amanieu d'Antras
4fe088329c Work around CI failures for the ARM target 
These seem to have been introduced by recent LLVM changes.

* The instruction limit for vld*/vst* has been raised. This is not a
significant issue, it is only used for testing.
* vld*/vst* instructions are generated with overly strict alignments:
https://github.com/rust-lang/stdarch/issues/1217
* vtbl/vtbx instrinsics are failing intrinsic-test for unknown reasons.
 2023-11-30 07:48:09 +00:00
Eduardo Sánchez Muñoz
9f741c5986 Simplify some expressions with pointers and references 2023-10-31 02:20:17 +01:00
Eduardo Sánchez Muñoz
5cdd9f81ce Convert while loop to for 2023-10-31 02:20:17 +01:00
Eduardo Sánchez Muñoz
8950416e20 Bump wasmprinter to 0.2.67 2023-10-10 14:47:43 +01:00
Gijs Burghoorn
0d56394f35 Fix: #1464 for rv64 zb 2023-09-22 10:08:56 +08:00
Gijs Burghoorn
8a23f93e8b Fix: #1464 for rv64 zk 2023-09-22 10:08:56 +08:00
Amanieu d'Antras
17daea9747 Update instruction tests for LLVM 17 2023-08-29 15:21:34 +02:00
Amanieu d'Antras
fff032b929 Fix CI on wasm32-wasi 
The cc dependency doesn't compile on wasi, so only include it for
windows targets.
 2023-08-29 15:21:34 +02:00
Jacob Bramley
f480c64fe9 Remove assert_instr exception for AArch64 *cvt*. 
The LLVM code generation was improved some time ago.
 2023-06-09 00:34:38 +02:00
Amanieu d'Antras
acee6b804a stdarch-test: Ignore {evex} prefix emitted by recent objdump 2023-04-08 21:41:40 +01:00
Alex Crichton
be861579df wasm32: Add relaxed simd instructions 
This commit adds intrinsics to the `wasm32` to support the [relaxed SIMD
proposal][proposal]. These are added with the same naming conventions of
existing simd-related intrinsics for wasm which is similar to the
instruction name but matches sign in a few places.

This additionally updates Wasmtime to execute tests with support for the
relaxed simd proposal. No release has been made yet so this uses the
`dev` release, and I can make a PR in April when the support in Wasmtime
has been released to an official release. The `wasmprinter` crate is
also updated to understand these instruction opcodes as well.

Documentation has been added for all intrinsics, but tests have only
been added for some of them so far. I hope to follow-up later with more
tests.

[proposal]: https://github.com/WebAssembly/relaxed-simd
 2023-03-19 16:08:18 +01:00
bwmf2
1c18225f32 Fix typo 2023-02-18 20:02:17 +01:00
Yuri Astrakhan
81c221f058
Edition 2021, apply clippy::uninlined_format_args fix (#1339) 2022-10-25 20:17:23 +01:00
Chris Wailes
13d20910b7
Update the Android Docker files to Ubuntu 22.04 (#1338) 2022-10-04 09:19:36 +01:00
Charles Lew
676d095f0a Bump cfg-if dependency to 1.0 2022-09-11 13:05:05 +02:00
Sparrow Li
68e35d306f
Complete vld* and vst* neon instructions (#1224) 2021-09-29 04:28:10 +01:00
Sparrow Li
bdea403c54
Complete vst1 neon instructions (#1221) 2021-09-24 13:26:29 +01:00
Hans Kratz
4f8ed0335c
Check inlining and instruction count for assert_instr(nop) as well (#1218) 2021-09-18 01:53:32 +01:00
Hans Kratz
5cd6850171
Normalize [us]shll.* ..., #0 aarch64 disassembly to the preferred [us]xtl.* (#1213) 2021-09-08 23:41:31 +01:00
Hans Kratz
bf2122753a Disable arm inlining check again for now as some tests are still failing. 2021-09-09 00:22:33 +02:00
Hans Kratz
5995d769ad Use a lighter dedup guard in the assert_instr test shims. 2021-09-09 00:22:33 +02:00
Hans Kratz
755e622d17 Implement proper subroutine call detection for x86, x86_64, aarch64 and wasm32. 2021-09-08 19:14:13 +02:00
Hans Kratz
03fa985cf0 remove assembly parsing special case for otool output (no longer needed) 2021-09-08 19:14:13 +02:00
Hans Kratz
999d954aa4 using v8.6a target feature to cover more instructions 2021-09-08 19:14:13 +02:00
Hans Kratz
f5af9d15a9 Use objdump on Macos x86_64 as well. 2021-09-08 19:14:13 +02:00
Hans Kratz
f15c851517 Use LLVM objdump on Macos ARM64 because it is not possible to enable TME support with otool 2021-09-08 19:14:13 +02:00
Sparrow Li
9e34c6d4c8
Add vst neon instructions (#1205) 
* add vst neon instructions

* modify the instruction limit
 2021-08-31 21:35:30 +01:00
Jamie Cunliffe
0285e513e0 Update arm vcvt intrinsics to use llvm.fpto(su)i.sat 
Those intrinsics have the correct semantics for the desired fcvtz instruction,
without any undefined behaviour. The previous simd_cast was undefined for
infinite and NaN which could cause issues.
 2021-08-11 13:13:19 +01:00
Sparrow Li
10f7ebc387
Add vfma and vfms neon instructions (#1169) 2021-05-21 12:26:21 +01:00
Sparrow Li
07f1d0cae3
Add vmla_n, vmla_lane, vmls_n, vmls_lane neon instructions (#1145) 2021-04-28 22:59:41 +01:00
surechen
d46e0086e4
add neon instruction vfma_n_* (#1122) 2021-04-17 17:45:54 +01:00
Sebastian Thiel
43126c3f65
[DRAFT] intrinsics for all architectures appear in rustdoc (#1104) 2021-04-17 13:46:33 +01:00
Sparrow Li
88a5de08cb
Allow primitive types in the code generator and add vdup instructions (#1114) 2021-04-12 14:08:26 +01:00
Joshua Nelson
b411a5c375
Convert all crates to 2018 edition (#1109) 2021-04-11 15:26:35 +01:00
Joshua Nelson
7bab2c0695
Deny 2018 idiom lints (#1108) 
This lint is allow by default, which is why this wasn't spotted earlier.
It's denied by rust-lang/rust, so it's good to warn about it here so it
can be fixed more quickly.
 2021-04-07 05:46:39 +01:00
Alex Crichton
e35da555f8
Update WebAssembly SIMD/Atomics (#1073) 2021-03-11 23:30:30 +00:00
Makoto Kato
9a4ff9fe79
Use --no-show-raw-insn to make disassemble parser simple. (#948) 2020-11-06 21:56:36 +00:00
Joseph Richey
e254082775
Use black_box instead of llvm_asm (#944) 
The implementation is the same (where possible), and it unblocks #904

Signed-off-by: Joe Richey <joerichey@google.com>
 2020-11-04 17:20:13 +00:00