- Disable `vsx` tests for `ppc` and `ppc64`
- Disable `tme` tests for `aarch64` and `aarch64_be`
- Disable `frecipe` tests for `loongarch64`
- Add `altivec` run for PPC32 (with `-C target-feature=+vsx` `qemu` gives a nasty error)
This is to combat the spurious CI failures in emulated run. Also helps with updatability and compatibility - it will work even if Intel changes the link
This commit is a replacement for #1417 now that rust-lang/rust#12046 has
landed. While I was here I went ahead and updated the Wasmtime used in
CI and adapted its command line as well.
This involves moving from the ACLE intrinsic definitions (which aren't
available for SVE at this point) to a JSON file. This was derived from
ARM's documentation[^1], and then relicensed under `MIT OR Apache-2.0` for
use in this repository.
[^1]: https://developer.arm.com/architectures/instruction-sets/intrinsics
This moves from the "dev" release of Wasmtime, used for its relaxed-simd
support, to an official release of Wasmtime just made which is the first
with relaxed-simd support.
This commit adds intrinsics to the `wasm32` to support the [relaxed SIMD
proposal][proposal]. These are added with the same naming conventions of
existing simd-related intrinsics for wasm which is similar to the
instruction name but matches sign in a few places.
This additionally updates Wasmtime to execute tests with support for the
relaxed simd proposal. No release has been made yet so this uses the
`dev` release, and I can make a PR in April when the support in Wasmtime
has been released to an official release. The `wasmprinter` crate is
also updated to understand these instruction opcodes as well.
Documentation has been added for all intrinsics, but tests have only
been added for some of them so far. I hope to follow-up later with more
tests.
[proposal]: https://github.com/WebAssembly/relaxed-simd
