1498 Commits

Author SHA1 Message Date
Sayantan Chakraborty
2922cbdd47
Merge pull request #1961 from folkertdev/pmadd-correct-signedness
correct signedness of pmadd arguments
2025-11-17 15:52:10 +00:00
Marco Ieni
2788686995
Merge pull request #1957 from marcoieni/rename-default-branch-to-main
rename default branch to main
2025-11-17 15:02:03 +00:00
Folkert de Vries
ac2d97254e
correct signedness of pmadd arguments 2025-11-17 16:01:02 +01:00
Folkert de Vries
57436fe950
Merge pull request #1960 from maurer/remove-tme
aarch64: Remove withdrawn FEAT_TME
2025-11-17 14:29:49 +00:00
sayantn
8fe87e9623
correct some #[simd_test] attributes 2025-11-17 01:24:03 +05:30
Matthew Maurer
0882a6e02a aarch64: Remove withdrawn FEAT_TME
ARM has withdrawn FEAT_TME
https://developer.arm.com/documentation/102105/lb-05/

LLVM has also dropped support for enabling the feature.
2025-11-14 19:25:34 +00:00
Folkert de Vries
d84c69548d
Merge pull request #1955 from sayantn/vector-shifts
Use SIMD intrinsics for vector shifts
2025-11-13 11:10:25 +00:00
Folkert de Vries
84c44c449d
Merge pull request #1959 from folkertdev/ternary-logic-tests-2
improve ternary logic tests
2025-11-13 09:41:34 +00:00
sayantn
0ab7c9e3da
Use SIMD intrinsics for vector shifts 2025-11-13 10:49:31 +05:30
Folkert de Vries
849ace0685
Merge pull request #1953 from sayantn/masked-load-store
Use generic SIMD masked load/stores for avx512 masked load/stores
2025-11-12 12:54:10 +00:00
Folkert de Vries
e94ac6b638
improve ternary logic tests 2025-11-11 17:04:11 +01:00
Folkert de Vries
148a7509a1
add logic tests for ternarylogic
previously the output would just always be all zeroes
2025-11-11 11:30:14 +01:00
MarcoIeni
1b3abfea94
rename default branch to main 2025-11-11 10:04:15 +01:00
The rustc-josh-sync Cronjob Bot
485ea04b6d Merge ref '8401398e1f14' from rust-lang/rust
Pull recent changes from https://github.com/rust-lang/rust via Josh.

Upstream ref: 8401398e1f14a24670ee1a3203713dc2f0f8b3a8
Filtered ref: f9e99a8e85fa360f0e820dc75d46cb4583b4300d
Upstream diff: 73e6c9ebd9...8401398e1f

This merge was created using https://github.com/rust-lang/josh-sync.
2025-11-10 04:10:16 +00:00
sayantn
7ea8483696
Use generic SIMD intrinsics for AVX maskload and maskstore intrinsics 2025-11-07 05:34:31 +05:30
Folkert de Vries
7516645928
stabilize s390x_target_feature_vector 2025-11-06 12:49:48 +01:00
Folkert de Vries
c59298da36
stabilize stdarch_s390x_feature_detection 2025-11-06 12:49:46 +01:00
Folkert de Vries
0645ac31cb
extract s390x vector and friends to their own rust feature 2025-11-06 12:49:04 +01:00
sayantn
9126145419
Use generic SIMD masked load/stores for avx512 masked load/stores 2025-11-05 21:30:48 +05:30
Amanieu d'Antras
591487758b
Merge pull request #1846 from sayantn/new-amx-intrinsics
Add intrinsics for the new AMX target features
2025-11-04 01:59:32 +00:00
Folkert de Vries
f9dc790aa5
improve _mm256_permute2f128 tests 2025-11-02 20:09:54 +01:00
Jakub Beránek
3c9656c4f4
Merge ref '73e6c9ebd912' from rust-lang/rust
Pull recent changes from https://github.com/rust-lang/rust via Josh.

Upstream ref: 73e6c9ebd9123154a196300ef58e30ec8928e74e
Filtered ref: e8bb3cae4cd2b04bdc252cdf79102717db2b2d8d
Upstream diff: 32e7a4b92b...73e6c9ebd9

This merge was created using https://github.com/rust-lang/josh-sync.
2025-11-02 14:45:26 +01:00
sayantn
17c3f8ab5e
Add tests for new AMX intrinsics 2025-11-01 07:55:34 +05:30
sayantn
48116cf39d
Add AMX intrinsics 2025-11-01 07:52:34 +05:30
Alisa Sireneva
420544a34a Move wasm throw intrinsic back to unwind
rustc assumes that regular `extern "Rust"` functions unwind only if the
`unwind` panic runtime is linked. `throw` was annotated as such, but
unwound unconditionally. This could cause UB when a crate built with `-C
panic=abort` called `throw` from `core` built with `-C panic=unwind`,
since no terminator was added to handle the panic arising from calling an
allegedly non-unwinding `extern "Rust"` function.

rustc was taught to recognize this condition since
https://github.com/rust-lang/rust/pull/144225 and prevented such
linkage, but this caused regressions in
https://github.com/rust-lang/rust/issues/148246, since this meant that
Emscripten projects could not be built with `-C panic=abort` without
recompiling std.

The most straightforward solution would be to move `throw` into the
`panic_unwind` crate, so that it's only compiled if the panic runtime is
guaranteed to be `unwind`, but this is messy due to our architecture.
Instead, move it into `unwind::wasm`, which is only compiled for
bare-metal targets that default to `panic = "abort"`, rendering the
issue moot.
2025-10-30 15:13:32 +03:00
Noa
a4638e3d25
Enable assert_instr for wasm32 throw 2025-10-27 12:12:52 -05:00
sayantn
4c6e879326
Make the fence intrinsics and _mm_pause safe 2025-10-26 23:57:47 +05:30
sayantn
22f169f844
Make _mm_prefetch safe 2025-10-26 23:57:42 +05:30
sayantn
8bff8b6849
Make all TBM intrinsics safe 2025-10-26 23:52:45 +05:30
sayantn
f2eb88b0bb
Make RDRAND/RDSEED safe 2025-10-26 23:52:45 +05:30
sayantn
5dcd3046c8
Make _bswap{,64} safe 2025-10-26 23:52:45 +05:30
sayantn
cfb36829a9
Make _mm512_reduce_mul_ph safe (missed) 2025-10-26 23:52:45 +05:30
sayantn
788d1826e9
Make ADC/ADX intrinsics safe 2025-10-26 23:52:44 +05:30
Folkert de Vries
cf1cf2e94d
remove a use of core::intrinsics::size_of
use of the intrinsic, rather than the stable function, is probably an accident.
2025-10-25 23:57:17 +02:00
Amanieu d'Antras
d64b23c061
Merge pull request #1945 from folkertdev/gfni-cleanup
use `byte_add` in gfni tests
2025-10-25 14:17:49 +00:00
Folkert de Vries
9ebee4853d
use byte_add in gfni tests 2025-10-25 01:55:37 +02:00
Folkert de Vries
8dff65f010
Merge pull request #1938 from linkmauve/fjcvtzs
Implement fjcvtzs under the name __jcvt like the C intrinsic
2025-10-10 14:13:13 +00:00
Emmanuel Gil Peyrot
6039ddea09 Implement fjcvtzs under the name __jcvt like the C intrinsic
This instruction is only available when the jsconv target_feature is available,
so on ARMv8.3 or higher.

It is used e.g. by Ruffle[0] to speed up its conversion from f64 to i32, or by
any JS engine probably.

I’ve picked the stdarch_aarch64_jscvt feature because it’s the name of the
FEAT_JSCVT, but hesitated with naming it stdarch_aarch64_jsconv (the name of
the target_feature) or stdarch_aarch64_jcvt (the name of the C intrinsic) or
stdarch_aarch64_fjcvtzs (the name of the instruction), this choice is purely
arbitrary and I guess it could be argued one way or another.  I wouldn’t expect
it to stay unstable for too long, so ultimately this shouldn’t matter much.

This feature is now tracked in this issue[1].

[0] https://github.com/ruffle-rs/ruffle/pull/21780
[1] https://github.com/rust-lang/rust/issues/147555
2025-10-10 13:29:42 +00:00
Sayantan Chakraborty
01dc34d709
Merge pull request #1939 from folkertdev/crc-remove-not-arm
crc32: remove `#[cfg(not(target_arch = "arm"))]` from aarch64 crc functions
2025-10-09 17:37:09 +00:00
Folkert de Vries
4fcf3f86c4
crc32: remove #[cfg(not(target_arch = "arm"))] from crc functions
They are defined in the aarch64 module, so this cfg is pointless.

Note that these instructions do exist for arm, but the aarch64 ones are
already stable, so this would need some additional work to implement
them for arm.
2025-10-09 19:20:20 +02:00
Folkert de Vries
27866a7f06
Merge pull request #1937 from sayantn/intrinsic-fixes
use simd intrinsics for `vec_max` and `vec_min`
2025-10-08 11:17:58 +00:00
sayantn
40ce617b2a
use simd intrinsics for vec_max and vec_min 2025-10-08 16:01:08 +05:30
Tsukasa OI
af91b45726 RISC-V: Use symbolic instructions on inline assembly (part 1)
While many intrinsics use `.insn` to generate raw machine code from
numbers, all ratified instructions can be symbolic
using `.option` directives.

By saving the assembler environment with `.option push` then modifying
the architecture with `.option arch`, we can temporarily enable certain
extensions (as we use `.option pop` immediately after the target
instruction, surrounding environment is completely intact in this
commit; *almost* completely intact in general).

This commit modifies the `pause` *hint* intrinsic to use symbolic
*instruction* because we want to expose it even if the Zihintpause
extension is unavailable on the target.
2025-10-06 01:08:42 +00:00
Amanieu d'Antras
09c43ef6d3
Merge pull request #1929 from sayantn/non-temporal
Fixes for non-temporal intrinsics
2025-10-05 22:44:09 +00:00
sayantn
c0e41518d1
Add comments in NT asm blocks for future reference 2025-10-05 07:04:36 +05:30
sayantn
5bf53654c5
Add _mm_sfence to all non-temporal intrinsic tests 2025-10-05 06:56:49 +05:30
sayantn
b29308c167
Use Inline ASM for SSE4a nontemporal stores 2025-10-05 06:56:46 +05:30
sayantn
28cf2d1a6c
Fix xsave segfaults 2025-10-05 05:39:29 +05:30
Sayantan Chakraborty
7e850c5f1e
Merge pull request #1932 from sayantn/fmaddsub
Use SIMD intrinsics for `vfmaddsubph` and `vfmsubaddph`
2025-10-04 00:43:02 +00:00
Amanieu d'Antras
14b888574f
Merge pull request #1931 from sayantn/use-intrinsics
Fix mistake in #1928
2025-10-03 13:10:34 +00:00