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1218 Commits

Author SHA1 Message Date
WANG Rui
f74fe05f9e core_arch: Add LoongArch LSX testcases 2024-02-28 08:43:52 +00:00
ZHAI Xiang
9a8f1dac0e core_arch: Add LoongArch LSX intrinsics 
Co-authored-by: WANG Rui <wangrui@loongson.cn>
 2024-02-28 08:43:52 +00:00
ZHAI Xiang
a66ae3ec9e Add intrinsic code generator for LoongArch 
Co-authored-by: WANG Rui <wangrui@loongson.cn>
 2024-02-28 08:43:52 +00:00
WANG Rui
6ecbc8ebfb stdarch-gen: Move to stdarch-gen-arm 2024-02-28 08:43:52 +00:00
Pavel Grigorenko
1c16ce54e5 use addr_of! 2024-02-24 23:12:18 +00:00
usamoi
8531e289b0 feat: std_detect avx512fp16 
Signed-off-by: usamoi <usamoi@outlook.com>
 2024-02-24 16:07:04 +00:00
Ralf Jung
da78357bf7 use remaining SIMD intrinsics via libcore 2024-02-23 22:32:49 +00:00
Luca Barbato
13bd2979fc Add vec_sel 2024-02-23 17:05:57 +00:00
Luca Barbato
0fe5dfb4be Add vec_nand 2024-02-23 17:05:57 +00:00
Ralf Jung
f5c0b76cf3 non-temporal stores: document interaction with Rust memory model 2024-02-21 00:54:27 +00:00
Amanieu d'Antras
975ba7f853 Fix redundant import warnings 
These were introduced by rust-lang/rust#117772.
 2024-02-20 23:21:06 +00:00
Ralf Jung
92a957da6d simplify simd_ty, simd_m_ty macros: do not repeat the element type N times 2024-02-18 16:25:51 +00:00
Ralf Jung
c064146098 remove unnecessary let binding 2024-02-18 15:33:30 +00:00
Ralf Jung
ff9ba664e1 avoid using simd_extract in SimdTy::extract (since the index is not a constant there) 2024-02-17 17:30:51 +00:00
Ralf Jung
229399be14 put the idx arguments of simd_insert and simd_extract into const blocks 2024-02-17 17:30:51 +00:00
Ralf Jung
2d84cf913c import LLVM SIMD intrinsics from core rather than declaring them locally 2024-02-17 12:15:49 +00:00
Adam Gemmell
e54a6d71bf Improve feature detect for combined aarch64 features 
LLVM's `ssbs` and `mte` target_features represent two Arm features.
Linux's HWCAP also represents the same two features, so this is just a
documentation update.

LLVM's `ras` target_feature represents two Arm features - FEAT_RAS and FEAT_RASv1p1. There is no runtime detection for this, so this is a no-op in stdarch.

LLVM's `aes` feature covers both `FEAT_AES` and `FEAT_PMULL`, but Linux
exposes seperate feature bits. This patch makes the `aes` target_feature
correctly shortcut runtime `pmull` detection and also makes the `aes`
feature check for `pmull` at runtime to bring it in line with the
target_feature behaviour. In practice I think this makes the two runtime
features identical since the ID_AA64ISAR0_EL1 register does not allow
for PMULL without AES.
 2024-02-16 18:21:34 +00:00
Luca Barbato
f866a61df6 Add vec_subc 2024-02-16 15:57:52 +00:00
Luca Barbato
e5d393dce8 Add vec_round 2024-02-16 15:57:52 +00:00
Luca Barbato
9dbcfa9856 Add vec_rl 2024-02-16 15:57:52 +00:00
Luca Barbato
6b6fb15fbb Add vec_cntlz 2024-02-16 15:57:52 +00:00
Nikita Popov
7f510b818f Update test expectations for aarch64 2024-02-16 10:55:33 +00:00
daxpedda
1e8274d34d Remove last mention of stdsimd 2024-02-14 15:08:29 +00:00
Luca Barbato
122674ff51 Add vec_st, vec_stl, vec_ste 2024-02-11 11:51:02 +00:00
Luca Barbato
77272548a7 Fix vec_ldl 2024-02-11 11:51:02 +00:00
Luca Barbato
848d0c4878 Add vec_cmpne 2024-01-29 16:00:22 +00:00
Luca Barbato
e216d66329 Add the boolean types for vec_nor 2024-01-29 16:00:22 +00:00
Luca Barbato
0e945675ca Add vec_adde 2024-01-29 16:00:22 +00:00
Luca Barbato
862009da89 Add vec_slv and vec_srv 2024-01-26 00:10:58 +00:00
Luca Barbato
1ffec54a84 Add vec_sro 2024-01-26 00:10:58 +00:00
Luca Barbato
e3745d93c9 Add vec_srl 2024-01-26 00:10:58 +00:00
Luca Barbato
5b58bae153 Add vec_sra 2024-01-26 00:10:58 +00:00
Luca Barbato
f5a65e7951 Add vec_sr 2024-01-26 00:10:58 +00:00
Luca Barbato
59fc60f983 Add vec_slo 2024-01-26 00:10:58 +00:00
Luca Barbato
2ae29d26a2 Add vec_sll 2024-01-26 00:10:58 +00:00
Luca Barbato
0da079d7a5 Add vec_sld and vec_sldw 2024-01-26 00:10:58 +00:00
Luca Barbato
2500f3b401 Add vec_sl 2024-01-26 00:10:58 +00:00
Makoto Kato
d51ea0d261 Add CPU detection for macOS/aarch64. 2024-01-16 02:57:10 +00:00
Luca Barbato
c4a00026d4 Rename vec_splat_i* to the correct name 2024-01-15 15:44:31 +00:00
eupn
2e8d4ba8c8
Add missing ARM-v7A CRC intrinsics (#1515) 
* Move aarch64 crc into arm shared module

* Add missing 32-bit arm crc intrinsics

On 32-bit ARM, this intrinsic emits two instructions and splits its 64-bit input parameter between them.

https://gcc.gnu.org/onlinedocs/gcc-4.9.4/gcc/ARM-ACLE-Intrinsics.html
 2024-01-10 12:44:04 +00:00
Luca Barbato
ea70e93c24 Add vec_xst 2024-01-06 00:40:31 +00:00
Amanieu d'Antras
76d52cdd68 Fix std_detect not being an unstable crate 
More fallout from #1486
 2024-01-05 11:14:38 +00:00
Amanieu d'Antras
fd973c2765 Fix std build failure on non-x86 architectures 
This is more fallout from #1486
 2024-01-04 13:00:34 +00:00
Amanieu d'Antras
a600c72f50 Fixes for use in the standard library 2024-01-02 17:46:10 +00:00
Amanieu d'Antras
b5406fedd4 Add #![allow(internal_features)] to a test to fix CI 2023-12-19 01:25:56 +00:00
Gijs Burghoorn
786f28dd8b Stabilize Ratified RISC-V Target Features 
As shortly discussed on Zulip
(https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions.

Specifically, this commit stabilizes the:
* Atomic Instructions (A) on v2.0
* Compressed Instructions (C) on v2.0
* Integer Multiplication and Division (M) on v2.0
* Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs`
* Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
 2023-11-30 22:53:04 +00:00
Amanieu d'Antras
3ac4ba6670 Revert "Work around CI failures for the ARM target" 
This reverts commit 5a748ec5fabcaee29351ac3c90eee4f3e16964e7.
 2023-11-30 08:20:47 +00:00
Jacob Bramley
86cb5730ae Report missing features when skipping tests. 2023-11-30 07:48:46 +00:00
Amanieu d'Antras
4fe088329c Work around CI failures for the ARM target 
These seem to have been introduced by recent LLVM changes.

* The instruction limit for vld*/vst* has been raised. This is not a
significant issue, it is only used for testing.
* vld*/vst* instructions are generated with overly strict alignments:
https://github.com/rust-lang/stdarch/issues/1217
* vtbl/vtbx instrinsics are failing intrinsic-test for unknown reasons.
 2023-11-30 07:48:09 +00:00
Eduardo Sánchez Muñoz
9b4a79c5d4 Re-implement some AVX functions without LLVM intrinsics 2023-11-18 20:30:18 -08:00