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Tsukasa OI 1c6d764b0b reword RISC-V feature documentation 
As the version 20240411 of the RISC-V ISA Manual changed wording to
describe many of the standard extensions, this commit largely follows this
scheme in general.  In many cases, words "Standard Extension" are replaced
with "Extension" following the latest ratified ISA Manual.

Some RISC-V extensions had tentative summary but it also fixes that
(e.g. "Zihintpause").

Following extensions are described in parity with corresponding extensions
using floating-point registers:

*   "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
*   "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
*   "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
*   "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers

Following extensions are named against the ISA Manual naming but
considered inconsistency inside the ISA manual:

*   "Zfhmin" Extension for Minimal Half-Precision Floating-Point
    ISA Manual: "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point
*   "V" Extension for Vector Operations
    ISA Manual: "V" Standard Extension for Vector Operations

Following extension is removed from the latest ratified ISA Manual but
named like others:

*   "Zam" Extension for Misaligned Atomics

"Zb*" extensions are described like "Extension for ..." using partial
summary per extension (including cryptography-related "Zbk*" extensions).

"Zk*" extensions are described like "Cryptography Extension for ..." using
partial summary per extension (e.g. 'Zkne - NIST Suite: AES Encryption' in
the ISA Manual to '"Zkne" Cryptography Extension for NIST Suite: AES
Encryption') except following extensions:

*   "Zkr" Entropy Source Extension
    Following the general rule will make the description redundant.
*   "Zk" Cryptography Extension for Standard scalar cryptography
    The last word "extension" is removed as seemed redundant.

Link:

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications>
(ISA Specifications, Version 20240411; published in May 2024)
2025-03-24 23:47:00 +00:00
..
src
reword RISC-V feature documentation
2025-03-24 23:47:00 +00:00
tests
Add runtime feature detection for keylocker
2025-02-13 10:54:53 +00:00
Cargo.toml
Update all crates to Rust 2024
2025-02-09 12:31:33 -08:00
LICENSE-APACHE
Readme from std_detect
2019-01-22 18:49:24 +01:00
LICENSE-MIT
Readme from std_detect
2019-01-22 18:49:24 +01:00
README.md
add is_s390x_feature_detected
2025-01-16 20:39:13 +00:00

README.md

std::detect - Rust's standard library run-time CPU feature detection

The private std::detect module implements run-time feature detection in Rust's standard library. This allows detecting whether the CPU the binary runs on supports certain features, like SIMD instructions.

Usage

std::detect APIs are available as part of libstd. Prefer using it via the standard library than through this crate. Unstable features of std::detect are available on nightly Rust behind various feature-gates.

If you need run-time feature detection in #[no_std] environments, Rust core library cannot help you. By design, Rust core is platform independent, but performing run-time feature detection requires a certain level of cooperation from the platform.

You can then manually include std_detect as a dependency to get similar run-time feature detection support than the one offered by Rust's standard library. We intend to make std_detect more flexible and configurable in this regard to better serve the needs of #[no_std] targets.

Features

  • std_detect_dlsym_getauxval (enabled by default, requires libc): Enable to use libc::dlsym to query whether getauxval is linked into the binary. When this is not the case, this feature allows other fallback methods to perform run-time feature detection. When this feature is disabled, std_detect assumes that getauxval is linked to the binary. If that is not the case the behavior is undefined.

    Note: This feature is ignored on *-linux-gnu* and *-android* targets because we can safely assume getauxval is linked to the binary.

  • std_detect_file_io (enabled by default, requires std): Enable to perform run-time feature detection using file APIs (e.g. /proc/cpuinfo, etc.) if other more performant methods fail. This feature requires libstd as a dependency, preventing the crate from working on applications in which std is not available.

Platform support

  • All x86/x86_64 targets are supported on all platforms by querying the cpuid instruction directly for the features supported by the hardware and the operating system. std_detect assumes that the binary is an user-space application. If you need raw support for querying cpuid, consider using the cupid crate.

  • Linux/Android:

    • arm{32, 64}, mips{32,64}{,el}, powerpc{32,64}{,le}, riscv{32,64}, loongarch64, s390x: std_detect supports these on Linux by querying ELF auxiliary vectors (using getauxval when available), and if that fails, by querying /proc/cpuinfo.
    • arm64: partial support for doing run-time feature detection by directly querying mrs is implemented for Linux >= 4.11, but not enabled by default.

  • FreeBSD:

    • arm32, powerpc64: std_detect supports these on FreeBSD by querying ELF auxiliary vectors using sysctl.
    • arm64: run-time feature detection is implemented by directly querying mrs.

  • OpenBSD:

    • arm64: run-time feature detection is implemented by querying sysctl.

  • Windows:

    • arm64: run-time feature detection is implemented by querying IsProcessorFeaturePresent.

License

This project is licensed under either of

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in std_detect by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.