mirror of
https://github.com/rust-lang/rust.git
synced 2025-10-03 02:40:40 +00:00
f34e30affa
rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register [in the reference](https://doc.rust-lang.org/reference/inline-assembly.html#r-asm.rules.preserved-registers), it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.