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Allow custom default address spaces and parse `p-` specifications in the datalayout string Some targets, such as CHERI, use as default an address space different from the "normal" default address space `0` (in the case of CHERI, [200 is used](https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-877.pdf)). Currently, `rustc` does not allow to specify custom address spaces and does not take into consideration [`p-` specifications in the datalayout string](https://llvm.org/docs/LangRef.html#langref-datalayout). This patch tries to mitigate these problems by allowing targets to define a custom default address space (while keeping the default value to address space `0`) and adding the code to parse the `p-` specifications in `rustc_abi`. The main changes are that `TargetDataLayout` now uses functions to refer to pointer-related informations, instead of having specific fields for the size and alignment of pointers in the default address space; furthermore, the two `pointer_size` and `pointer_align` fields in `TargetDataLayout` are replaced with an `FxHashMap` that holds info for all the possible address spaces, as parsed by the `p-` specifications. The potential performance drawbacks of not having ad-hoc fields for the default address space will be tested in this PR's CI run. r? workingjubilee
233 lines
8.6 KiB
Rust
233 lines
8.6 KiB
Rust
use rustc_abi::{
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AddressSpace, Align, BackendRepr, HasDataLayout, Primitive, Reg, RegKind, TyAbiInterface,
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TyAndLayout,
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};
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use crate::callconv::{ArgAttribute, FnAbi, PassMode};
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use crate::spec::{HasTargetSpec, RustcAbi};
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#[derive(PartialEq)]
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pub(crate) enum Flavor {
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General,
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FastcallOrVectorcall,
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}
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pub(crate) struct X86Options {
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pub flavor: Flavor,
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pub regparm: Option<u32>,
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pub reg_struct_return: bool,
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}
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pub(crate) fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>, opts: X86Options)
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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C: HasDataLayout + HasTargetSpec,
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{
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if !fn_abi.ret.is_ignore() {
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if fn_abi.ret.layout.is_aggregate() && fn_abi.ret.layout.is_sized() {
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// Returning a structure. Most often, this will use
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// a hidden first argument. On some platforms, though,
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// small structs are returned as integers.
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//
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// Some links:
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// https://www.angelcode.com/dev/callconv/callconv.html
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// Clang's ABI handling is in lib/CodeGen/TargetInfo.cpp
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let t = cx.target_spec();
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if t.abi_return_struct_as_int || opts.reg_struct_return {
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// According to Clang, everyone but MSVC returns single-element
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// float aggregates directly in a floating-point register.
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if fn_abi.ret.layout.is_single_fp_element(cx) {
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match fn_abi.ret.layout.size.bytes() {
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4 => fn_abi.ret.cast_to(Reg::f32()),
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8 => fn_abi.ret.cast_to(Reg::f64()),
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_ => fn_abi.ret.make_indirect(),
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}
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} else {
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match fn_abi.ret.layout.size.bytes() {
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1 => fn_abi.ret.cast_to(Reg::i8()),
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2 => fn_abi.ret.cast_to(Reg::i16()),
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4 => fn_abi.ret.cast_to(Reg::i32()),
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8 => fn_abi.ret.cast_to(Reg::i64()),
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_ => fn_abi.ret.make_indirect(),
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}
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}
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} else {
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fn_abi.ret.make_indirect();
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}
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} else {
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fn_abi.ret.extend_integer_width_to(32);
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}
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}
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for arg in fn_abi.args.iter_mut() {
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if arg.is_ignore() || !arg.layout.is_sized() {
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continue;
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}
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let t = cx.target_spec();
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let align_4 = Align::from_bytes(4).unwrap();
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let align_16 = Align::from_bytes(16).unwrap();
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if arg.layout.is_aggregate() {
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// We need to compute the alignment of the `byval` argument. The rules can be found in
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// `X86_32ABIInfo::getTypeStackAlignInBytes` in Clang's `TargetInfo.cpp`. Summarized
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// here, they are:
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//
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// 1. If the natural alignment of the type is <= 4, the alignment is 4.
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//
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// 2. Otherwise, on Linux, the alignment of any vector type is the natural alignment.
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// This doesn't matter here because we only pass aggregates via `byval`, not vectors.
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//
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// 3. Otherwise, on Apple platforms, the alignment of anything that contains a vector
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// type is 16.
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//
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// 4. If none of these conditions are true, the alignment is 4.
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fn contains_vector<'a, Ty, C>(cx: &C, layout: TyAndLayout<'a, Ty>) -> bool
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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{
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match layout.backend_repr {
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BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) => false,
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BackendRepr::SimdVector { .. } => true,
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BackendRepr::Memory { .. } => {
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for i in 0..layout.fields.count() {
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if contains_vector(cx, layout.field(cx, i)) {
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return true;
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}
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}
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false
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}
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}
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}
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let byval_align = if arg.layout.align.abi < align_4 {
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// (1.)
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align_4
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} else if t.is_like_darwin && contains_vector(cx, arg.layout) {
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// (3.)
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align_16
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} else {
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// (4.)
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align_4
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};
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arg.pass_by_stack_offset(Some(byval_align));
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} else {
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arg.extend_integer_width_to(32);
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}
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}
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fill_inregs(cx, fn_abi, opts, false);
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}
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pub(crate) fn fill_inregs<'a, Ty, C>(
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cx: &C,
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fn_abi: &mut FnAbi<'a, Ty>,
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opts: X86Options,
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rust_abi: bool,
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) where
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Ty: TyAbiInterface<'a, C> + Copy,
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{
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if opts.flavor != Flavor::FastcallOrVectorcall && opts.regparm.is_none_or(|x| x == 0) {
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return;
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}
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// Mark arguments as InReg like clang does it,
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// so our fastcall/vectorcall is compatible with C/C++ fastcall/vectorcall.
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// Clang reference: lib/CodeGen/TargetInfo.cpp
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// See X86_32ABIInfo::shouldPrimitiveUseInReg(), X86_32ABIInfo::updateFreeRegs()
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// IsSoftFloatABI is only set to true on ARM platforms,
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// which in turn can't be x86?
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// 2 for fastcall/vectorcall, regparm limited by 3 otherwise
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let mut free_regs = opts.regparm.unwrap_or(2).into();
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// For types generating PassMode::Cast, InRegs will not be set.
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// Maybe, this is a FIXME
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let has_casts = fn_abi.args.iter().any(|arg| matches!(arg.mode, PassMode::Cast { .. }));
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if has_casts && rust_abi {
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return;
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}
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for arg in fn_abi.args.iter_mut() {
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let attrs = match arg.mode {
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PassMode::Ignore | PassMode::Indirect { attrs: _, meta_attrs: None, on_stack: _ } => {
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continue;
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}
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PassMode::Direct(ref mut attrs) => attrs,
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PassMode::Pair(..)
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| PassMode::Indirect { attrs: _, meta_attrs: Some(_), on_stack: _ }
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| PassMode::Cast { .. } => {
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unreachable!("x86 shouldn't be passing arguments by {:?}", arg.mode)
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}
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};
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// At this point we know this must be a primitive of sorts.
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let unit = arg.layout.homogeneous_aggregate(cx).unwrap().unit().unwrap();
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assert_eq!(unit.size, arg.layout.size);
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if matches!(unit.kind, RegKind::Float | RegKind::Vector) {
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continue;
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}
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let size_in_regs = arg.layout.size.bits().div_ceil(32);
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if size_in_regs == 0 {
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continue;
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}
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if size_in_regs > free_regs {
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break;
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}
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free_regs -= size_in_regs;
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if arg.layout.size.bits() <= 32 && unit.kind == RegKind::Integer {
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attrs.set(ArgAttribute::InReg);
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}
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if free_regs == 0 {
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break;
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}
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}
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}
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pub(crate) fn compute_rust_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>)
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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C: HasDataLayout + HasTargetSpec,
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{
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// Avoid returning floats in x87 registers on x86 as loading and storing from x87
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// registers will quiet signalling NaNs. Also avoid using SSE registers since they
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// are not always available (depending on target features).
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if !fn_abi.ret.is_ignore() {
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let has_float = match fn_abi.ret.layout.backend_repr {
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BackendRepr::Scalar(s) => matches!(s.primitive(), Primitive::Float(_)),
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BackendRepr::ScalarPair(s1, s2) => {
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matches!(s1.primitive(), Primitive::Float(_))
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|| matches!(s2.primitive(), Primitive::Float(_))
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}
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_ => false, // anyway not passed via registers on x86
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};
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if has_float {
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if cx.target_spec().rustc_abi == Some(RustcAbi::X86Sse2)
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&& fn_abi.ret.layout.backend_repr.is_scalar()
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&& fn_abi.ret.layout.size.bits() <= 128
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{
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// This is a single scalar that fits into an SSE register, and the target uses the
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// SSE ABI. We prefer this over integer registers as float scalars need to be in SSE
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// registers for float operations, so that's the best place to pass them around.
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fn_abi.ret.cast_to(Reg { kind: RegKind::Vector, size: fn_abi.ret.layout.size });
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} else if fn_abi.ret.layout.size <= Primitive::Pointer(AddressSpace::ZERO).size(cx) {
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// Same size or smaller than pointer, return in an integer register.
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fn_abi.ret.cast_to(Reg { kind: RegKind::Integer, size: fn_abi.ret.layout.size });
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} else {
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// Larger than a pointer, return indirectly.
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fn_abi.ret.make_indirect();
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}
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return;
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}
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}
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}
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