rust/tests/mir-opt/pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir
Wesley Wiser 298ec5258f Disable MIR SROA optimization by default
Turn off the MIR SROA optimization by default to prevent incorrect
debuginfo generation and rustc ICEs caused by invalid LLVM IR being
created.

Related to #115113
2023-08-23 14:08:43 -04:00

54 lines
1.4 KiB
Rust

// MIR for `mem_replace` after PreCodegen
fn mem_replace(_1: &mut u32, _2: u32) -> u32 {
debug r => _1;
debug v => _2;
let mut _0: u32;
scope 1 (inlined std::mem::replace::<u32>) {
debug dest => _1;
debug src => _2;
let mut _3: *const u32;
let mut _4: *mut u32;
scope 2 {
scope 3 {
debug result => _0;
scope 7 (inlined std::ptr::write::<u32>) {
debug dst => _4;
debug src => _2;
let mut _6: *mut u32;
scope 8 {
scope 9 (inlined std::ptr::write::runtime::<u32>) {
debug dst => _6;
}
}
}
}
scope 4 (inlined std::ptr::read::<u32>) {
debug src => _3;
let mut _5: *const u32;
scope 5 {
scope 6 (inlined std::ptr::read::runtime::<u32>) {
debug src => _5;
}
}
}
}
}
bb0: {
StorageLive(_3);
_3 = &raw const (*_1);
StorageLive(_5);
_0 = (*_3);
StorageDead(_5);
StorageDead(_3);
StorageLive(_4);
_4 = &raw mut (*_1);
StorageLive(_6);
(*_4) = _2;
StorageDead(_6);
StorageDead(_4);
return;
}
}