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60 lines
1.8 KiB
Rust
60 lines
1.8 KiB
Rust
// verify that simd mask reductions do not introduce additional bit shift operations
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//@ add-core-stubs
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//@ revisions: x86 aarch64
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//@ [x86] compile-flags: --target=x86_64-unknown-linux-gnu -C llvm-args=-x86-asm-syntax=intel
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// Set the base cpu explicitly, in case the default has been changed.
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//@ [x86] compile-flags: -C target-cpu=x86-64
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//@ [x86] needs-llvm-components: x86
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//@ [aarch64] compile-flags: --target=aarch64-unknown-linux-gnu
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//@ [aarch64] needs-llvm-components: aarch64
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//@ assembly-output: emit-asm
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//@ compile-flags: --crate-type=lib -Copt-level=3 -C panic=abort
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#![feature(no_core, lang_items, repr_simd, intrinsics)]
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#![no_core]
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#![allow(non_camel_case_types)]
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extern crate minicore;
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use minicore::*;
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#[repr(simd)]
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pub struct mask8x16([i8; 16]);
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#[rustc_intrinsic]
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unsafe fn simd_reduce_all<T>(x: T) -> bool;
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#[rustc_intrinsic]
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unsafe fn simd_reduce_any<T>(x: T) -> bool;
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// CHECK-LABEL: mask_reduce_all:
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#[no_mangle]
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pub unsafe extern "C" fn mask_reduce_all(m: mask8x16) -> bool {
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// x86-NOT: psllw
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// x86: pmovmskb eax, xmm0
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// x86-NEXT: {{cmp ax, -1|cmp eax, 65535|xor eax, 65535}}
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// x86-NEXT: sete al
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//
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// aarch64-NOT: shl
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// aarch64: cmge v0.16b, v0.16b, #0
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// aarch64-DAG: mov [[REG1:[a-z0-9]+]], #1
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// aarch64-DAG: umaxv b0, v0.16b
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// aarch64-NEXT: fmov [[REG2:[a-z0-9]+]], s0
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// aarch64-NEXT: bic w0, [[REG1]], [[REG2]]
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simd_reduce_all(m)
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}
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// CHECK-LABEL: mask_reduce_any:
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#[no_mangle]
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pub unsafe extern "C" fn mask_reduce_any(m: mask8x16) -> bool {
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// x86-NOT: psllw
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// x86: pmovmskb
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// x86-NEXT: test eax, eax
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// x86-NEXT: setne al
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//
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// aarch64-NOT: shl
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// aarch64: cmlt v0.16b, v0.16b, #0
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// aarch64-NEXT: umaxv b0, v0.16b
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// aarch64-NEXT: fmov [[REG:[a-z0-9]+]], s0
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// aarch64-NEXT: and w0, [[REG]], #0x1
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simd_reduce_any(m)
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}
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