Eduardo Sánchez Muñoz 5c20a68339 Reimplement _mm256_addsub_ps and _mm256_addsub_pd without LLVM intrinsics

2023-10-10 14:48:55 +01:00

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aarch64

Update instruction tests for LLVM 17

2023-08-29 15:21:34 +02:00

arm

Remove redundant definitions

2023-07-30 08:00:01 +01:00

arm_shared

Add parentheses to avoid (re)parsing ambiguity in test_vsri macro.

2023-10-02 21:29:51 +01:00

mips

Replace associated const hacks with inline consts

2023-03-05 18:00:21 +01:00

nvptx

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powerpc

Add vec_xl

2023-07-03 20:39:57 +01:00

powerpc64

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riscv32

Fix: Remove assert_instr for RISCV, see #1464

2023-08-31 23:12:32 +02:00

riscv64

Add missing aes64im of RISC-V Zk extension

2023-09-25 10:36:24 +08:00

riscv_shared

Fix: #1464 for rv64 zb

2023-09-22 10:08:56 +08:00

wasm32

clippy: Some simple clippy fixes.

2023-07-30 10:58:50 +01:00

x86

Reimplement _mm256_addsub_ps and _mm256_addsub_pd without LLVM intrinsics

2023-10-10 14:48:55 +01:00

x86_64

Add #[cfg_attr(miri, ignore)] to SSE and SSE2 that cannot be supported by Miri

2023-10-02 21:29:51 +01:00

core_arch_docs.md

Update Intel Intrinsics Guide links

2023-02-18 20:34:16 +01:00

lib.rs

Add #![allow(internal_unstable)]

2023-08-29 15:21:34 +02:00

macros.rs

Replace associated const hacks with inline consts

2023-03-05 18:00:21 +01:00

mod.rs

Implement RISC-V Zk extension intrinsics

2023-08-31 23:12:32 +02:00

simd_llvm.rs

Remove simd_shuffle<n> usage in favor of simd_shuffle

2022-09-06 03:36:27 +02:00

simd.rs

Update the intrinsic checker tool (#1258)

2021-12-04 13:03:30 +00:00

v64.rs

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