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30962e58e6
* fix build after stabilization of cfg_target_feature and target_feature * fix doc tests * fix spurious unused_attributes warning * fix more unused attribute warnings * More unnecessary target features * Remove no longer needed trait imports * Remove fixed upstream workarounds * Fix parsing the #[assert_instr] macro Following upstream proc_macro changes * Fix form and parsing of #[simd_test] * Don't use Cargo features for testing modes Instead use RUSTFLAGS with `--cfg`. This'll help us be compatible with the latest Cargo where a tweak to workspaces and features made the previous invocations we had invalid. * Don't thread RUSTFLAGS through docker * Re-gate on x86 verification Closes #411
78 lines
2.4 KiB
Rust
78 lines
2.4 KiB
Rust
//! RDTSC instructions.
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#[cfg(test)]
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use stdsimd_test::assert_instr;
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/// Reads the current value of the processor’s time-stamp counter.
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///
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/// The processor monotonically increments the time-stamp counter MSR
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/// every clock cycle and resets it to 0 whenever the processor is
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/// reset.
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///
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/// The RDTSC instruction is not a serializing instruction. It does
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/// not necessarily wait until all previous instructions have been
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/// executed before reading the counter. Similarly, subsequent
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/// instructions may begin execution before the read operation is
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/// performed.
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///
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/// On processors that support the Intel 64 architecture, the
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/// high-order 32 bits of each of RAX and RDX are cleared.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_rdtsc)
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#[inline]
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#[cfg_attr(test, assert_instr(rdtsc))]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _rdtsc() -> i64 {
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rdtsc()
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}
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/// Reads the current value of the processor’s time-stamp counter and
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/// the `IA32_TSC_AUX MSR`.
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///
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/// The processor monotonically increments the time-stamp counter MSR
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/// every clock cycle and resets it to 0 whenever the processor is
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/// reset.
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///
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/// The RDTSCP instruction waits until all previous instructions have
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/// been executed before reading the counter. However, subsequent
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/// instructions may begin execution before the read operation is
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/// performed.
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///
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/// On processors that support the Intel 64 architecture, the
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/// high-order 32 bits of each of RAX, RDX, and RCX are cleared.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__rdtscp)
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#[inline]
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#[cfg_attr(test, assert_instr(rdtscp))]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn __rdtscp(aux: *mut u32) -> u64 {
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rdtscp(aux as *mut _)
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}
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#[allow(improper_ctypes)]
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extern "C" {
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#[link_name = "llvm.x86.rdtsc"]
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fn rdtsc() -> i64;
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#[link_name = "llvm.x86.rdtscp"]
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fn rdtscp(aux: *mut u8) -> u64;
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}
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#[cfg(test)]
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mod tests {
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use coresimd::x86::rdtsc;
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use stdsimd_test::simd_test;
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#[simd_test(enable = "sse2")]
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unsafe fn _rdtsc() {
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let r = rdtsc::_rdtsc();
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assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
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}
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#[simd_test(enable = "sse2")]
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unsafe fn _rdtscp() {
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let mut aux = 0;
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let r = rdtsc::__rdtscp(&mut aux);
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assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
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}
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}
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