mirror of
https://github.com/rust-lang/rust.git
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1031 lines
44 KiB
Rust
1031 lines
44 KiB
Rust
use crate::builder::Builder;
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use crate::context::CodegenCx;
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use crate::llvm;
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use crate::type_::Type;
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use crate::type_of::LayoutLlvmExt;
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use crate::value::Value;
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use rustc_ast::LlvmAsmDialect;
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use rustc_ast::{InlineAsmOptions, InlineAsmTemplatePiece};
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use rustc_codegen_ssa::mir::operand::OperandValue;
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use rustc_codegen_ssa::mir::place::PlaceRef;
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use rustc_codegen_ssa::traits::*;
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use rustc_data_structures::fx::FxHashMap;
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use rustc_hir as hir;
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use rustc_middle::ty::layout::TyAndLayout;
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use rustc_middle::{bug, span_bug};
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use rustc_span::{Pos, Span, Symbol};
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use rustc_target::abi::*;
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use rustc_target::asm::*;
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use libc::{c_char, c_uint};
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use tracing::debug;
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impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
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fn codegen_llvm_inline_asm(
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&mut self,
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ia: &hir::LlvmInlineAsmInner,
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outputs: Vec<PlaceRef<'tcx, &'ll Value>>,
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mut inputs: Vec<&'ll Value>,
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span: Span,
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) -> bool {
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let mut ext_constraints = vec![];
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let mut output_types = vec![];
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// Prepare the output operands
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let mut indirect_outputs = vec![];
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for (i, (out, &place)) in ia.outputs.iter().zip(&outputs).enumerate() {
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if out.is_rw {
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let operand = self.load_operand(place);
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if let OperandValue::Immediate(_) = operand.val {
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inputs.push(operand.immediate());
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}
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ext_constraints.push(i.to_string());
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}
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if out.is_indirect {
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let operand = self.load_operand(place);
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if let OperandValue::Immediate(_) = operand.val {
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indirect_outputs.push(operand.immediate());
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}
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} else {
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output_types.push(place.layout.llvm_type(self.cx));
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}
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}
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if !indirect_outputs.is_empty() {
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indirect_outputs.extend_from_slice(&inputs);
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inputs = indirect_outputs;
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}
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let clobbers = ia.clobbers.iter().map(|s| format!("~{{{}}}", &s));
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// Default per-arch clobbers
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// Basically what clang does
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let arch_clobbers = match &self.sess().target.arch[..] {
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"x86" | "x86_64" => &["~{dirflag}", "~{fpsr}", "~{flags}"][..],
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"mips" | "mips64" => &["~{$1}"],
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_ => &[],
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};
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let all_constraints = ia
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.outputs
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.iter()
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.map(|out| out.constraint.to_string())
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.chain(ia.inputs.iter().map(|s| s.to_string()))
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.chain(ext_constraints)
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.chain(clobbers)
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.chain(arch_clobbers.iter().map(|s| (*s).to_string()))
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.collect::<Vec<String>>()
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.join(",");
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debug!("Asm Constraints: {}", &all_constraints);
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// Depending on how many outputs we have, the return type is different
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let num_outputs = output_types.len();
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let output_type = match num_outputs {
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0 => self.type_void(),
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1 => output_types[0],
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_ => self.type_struct(&output_types, false),
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};
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let asm = ia.asm.as_str();
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let r = inline_asm_call(
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self,
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&asm,
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&all_constraints,
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&inputs,
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output_type,
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ia.volatile,
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ia.alignstack,
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ia.dialect,
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&[span],
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);
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if r.is_none() {
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return false;
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}
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let r = r.unwrap();
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// Again, based on how many outputs we have
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let outputs = ia.outputs.iter().zip(&outputs).filter(|&(o, _)| !o.is_indirect);
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for (i, (_, &place)) in outputs.enumerate() {
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let v = if num_outputs == 1 { r } else { self.extract_value(r, i as u64) };
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OperandValue::Immediate(v).store(self, place);
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}
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true
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}
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fn codegen_inline_asm(
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&mut self,
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template: &[InlineAsmTemplatePiece],
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operands: &[InlineAsmOperandRef<'tcx, Self>],
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options: InlineAsmOptions,
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line_spans: &[Span],
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) {
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let asm_arch = self.tcx.sess.asm_arch.unwrap();
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// Collect the types of output operands
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let mut constraints = vec![];
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let mut clobbers = vec![];
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let mut output_types = vec![];
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let mut op_idx = FxHashMap::default();
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let mut clobbered_x87 = false;
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for (idx, op) in operands.iter().enumerate() {
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match *op {
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InlineAsmOperandRef::Out { reg, late, place } => {
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let is_target_supported = |reg_class: InlineAsmRegClass| {
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for &(_, feature) in reg_class.supported_types(asm_arch) {
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if let Some(feature) = feature {
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if self.tcx.sess.target_features.contains(&Symbol::intern(feature))
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{
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return true;
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}
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} else {
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// Register class is unconditionally supported
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return true;
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}
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}
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false
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};
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let mut layout = None;
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let ty = if let Some(ref place) = place {
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layout = Some(&place.layout);
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llvm_fixup_output_type(self.cx, reg.reg_class(), &place.layout)
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} else if matches!(
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reg.reg_class(),
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InlineAsmRegClass::X86(
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X86InlineAsmRegClass::mmx_reg | X86InlineAsmRegClass::x87_reg
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)
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) {
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// Special handling for x87/mmx registers: we always
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// clobber the whole set if one register is marked as
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// clobbered. This is due to the way LLVM handles the
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// FP stack in inline assembly.
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if !clobbered_x87 {
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clobbered_x87 = true;
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clobbers.push("~{st}".to_string());
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for i in 1..=7 {
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clobbers.push(format!("~{{st({})}}", i));
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}
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}
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continue;
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} else if !is_target_supported(reg.reg_class())
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|| reg.reg_class().is_clobber_only(asm_arch)
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{
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// We turn discarded outputs into clobber constraints
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// if the target feature needed by the register class is
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// disabled. This is necessary otherwise LLVM will try
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// to actually allocate a register for the dummy output.
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assert!(matches!(reg, InlineAsmRegOrRegClass::Reg(_)));
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clobbers.push(format!("~{}", reg_to_llvm(reg, None)));
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continue;
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} else {
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// If the output is discarded, we don't really care what
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// type is used. We're just using this to tell LLVM to
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// reserve the register.
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dummy_output_type(self.cx, reg.reg_class())
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};
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output_types.push(ty);
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op_idx.insert(idx, constraints.len());
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let prefix = if late { "=" } else { "=&" };
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constraints.push(format!("{}{}", prefix, reg_to_llvm(reg, layout)));
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}
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InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => {
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let layout = if let Some(ref out_place) = out_place {
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&out_place.layout
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} else {
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// LLVM required tied operands to have the same type,
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// so we just use the type of the input.
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&in_value.layout
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};
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let ty = llvm_fixup_output_type(self.cx, reg.reg_class(), layout);
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output_types.push(ty);
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op_idx.insert(idx, constraints.len());
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let prefix = if late { "=" } else { "=&" };
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constraints.push(format!("{}{}", prefix, reg_to_llvm(reg, Some(layout))));
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}
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_ => {}
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}
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}
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// Collect input operands
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let mut inputs = vec![];
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for (idx, op) in operands.iter().enumerate() {
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match *op {
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InlineAsmOperandRef::In { reg, value } => {
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let llval =
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llvm_fixup_input(self, value.immediate(), reg.reg_class(), &value.layout);
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inputs.push(llval);
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op_idx.insert(idx, constraints.len());
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constraints.push(reg_to_llvm(reg, Some(&value.layout)));
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}
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InlineAsmOperandRef::InOut { reg, late: _, in_value, out_place: _ } => {
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let value = llvm_fixup_input(
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self,
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in_value.immediate(),
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reg.reg_class(),
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&in_value.layout,
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);
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inputs.push(value);
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constraints.push(format!("{}", op_idx[&idx]));
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}
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InlineAsmOperandRef::SymFn { instance } => {
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inputs.push(self.cx.get_fn(instance));
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op_idx.insert(idx, constraints.len());
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constraints.push("s".to_string());
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}
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InlineAsmOperandRef::SymStatic { def_id } => {
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inputs.push(self.cx.get_static(def_id));
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op_idx.insert(idx, constraints.len());
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constraints.push("s".to_string());
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}
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_ => {}
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}
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}
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// Build the template string
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let mut template_str = String::new();
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for piece in template {
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match *piece {
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InlineAsmTemplatePiece::String(ref s) => {
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if s.contains('$') {
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for c in s.chars() {
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if c == '$' {
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template_str.push_str("$$");
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} else {
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template_str.push(c);
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}
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}
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} else {
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template_str.push_str(s)
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}
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}
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InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
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match operands[operand_idx] {
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InlineAsmOperandRef::In { reg, .. }
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| InlineAsmOperandRef::Out { reg, .. }
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| InlineAsmOperandRef::InOut { reg, .. } => {
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let modifier = modifier_to_llvm(asm_arch, reg.reg_class(), modifier);
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if let Some(modifier) = modifier {
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template_str.push_str(&format!(
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"${{{}:{}}}",
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op_idx[&operand_idx], modifier
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));
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} else {
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template_str.push_str(&format!("${{{}}}", op_idx[&operand_idx]));
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}
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}
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InlineAsmOperandRef::Const { ref string } => {
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// Const operands get injected directly into the template
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template_str.push_str(string);
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}
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InlineAsmOperandRef::SymFn { .. }
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| InlineAsmOperandRef::SymStatic { .. } => {
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// Only emit the raw symbol name
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template_str.push_str(&format!("${{{}:c}}", op_idx[&operand_idx]));
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}
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}
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}
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}
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}
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constraints.append(&mut clobbers);
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if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
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match asm_arch {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
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constraints.push("~{cc}".to_string());
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}
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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constraints.extend_from_slice(&[
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"~{dirflag}".to_string(),
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"~{fpsr}".to_string(),
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"~{flags}".to_string(),
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]);
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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constraints.extend_from_slice(&[
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"~{vtype}".to_string(),
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"~{vl}".to_string(),
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"~{vxsat}".to_string(),
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"~{vxrm}".to_string(),
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]);
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}
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InlineAsmArch::Nvptx64 => {}
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InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
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InlineAsmArch::Hexagon => {}
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
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InlineAsmArch::S390x => {}
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InlineAsmArch::SpirV => {}
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InlineAsmArch::Wasm32 => {}
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InlineAsmArch::Bpf => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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// This is actually ignored by LLVM, but it's probably best to keep
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// it just in case. LLVM instead uses the ReadOnly/ReadNone
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// attributes on the call instruction to optimize.
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constraints.push("~{memory}".to_string());
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}
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let volatile = !options.contains(InlineAsmOptions::PURE);
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let alignstack = !options.contains(InlineAsmOptions::NOSTACK);
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let output_type = match &output_types[..] {
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[] => self.type_void(),
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[ty] => ty,
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tys => self.type_struct(tys, false),
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};
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let dialect = match asm_arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64
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if !options.contains(InlineAsmOptions::ATT_SYNTAX) =>
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{
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LlvmAsmDialect::Intel
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}
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_ => LlvmAsmDialect::Att,
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};
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let result = inline_asm_call(
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self,
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&template_str,
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&constraints.join(","),
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&inputs,
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output_type,
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volatile,
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alignstack,
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dialect,
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line_spans,
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)
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.unwrap_or_else(|| span_bug!(line_spans[0], "LLVM asm constraint validation failed"));
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if options.contains(InlineAsmOptions::PURE) {
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if options.contains(InlineAsmOptions::NOMEM) {
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llvm::Attribute::ReadNone.apply_callsite(llvm::AttributePlace::Function, result);
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} else if options.contains(InlineAsmOptions::READONLY) {
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llvm::Attribute::ReadOnly.apply_callsite(llvm::AttributePlace::Function, result);
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}
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llvm::Attribute::WillReturn.apply_callsite(llvm::AttributePlace::Function, result);
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} else if options.contains(InlineAsmOptions::NOMEM) {
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llvm::Attribute::InaccessibleMemOnly
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.apply_callsite(llvm::AttributePlace::Function, result);
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} else {
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// LLVM doesn't have an attribute to represent ReadOnly + SideEffect
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}
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// Write results to outputs
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for (idx, op) in operands.iter().enumerate() {
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if let InlineAsmOperandRef::Out { reg, place: Some(place), .. }
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| InlineAsmOperandRef::InOut { reg, out_place: Some(place), .. } = *op
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{
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let value = if output_types.len() == 1 {
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result
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} else {
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self.extract_value(result, op_idx[&idx] as u64)
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};
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let value = llvm_fixup_output(self, value, reg.reg_class(), &place.layout);
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OperandValue::Immediate(value).store(self, place);
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}
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}
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}
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}
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impl AsmMethods for CodegenCx<'ll, 'tcx> {
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fn codegen_global_asm(
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&self,
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template: &[InlineAsmTemplatePiece],
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operands: &[GlobalAsmOperandRef],
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options: InlineAsmOptions,
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_line_spans: &[Span],
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) {
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let asm_arch = self.tcx.sess.asm_arch.unwrap();
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|
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// Default to Intel syntax on x86
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let intel_syntax = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64)
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&& !options.contains(InlineAsmOptions::ATT_SYNTAX);
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|
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// Build the template string
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let mut template_str = String::new();
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if intel_syntax {
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template_str.push_str(".intel_syntax\n");
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}
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for piece in template {
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match *piece {
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InlineAsmTemplatePiece::String(ref s) => template_str.push_str(s),
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InlineAsmTemplatePiece::Placeholder { operand_idx, modifier: _, span: _ } => {
|
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match operands[operand_idx] {
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GlobalAsmOperandRef::Const { ref string } => {
|
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// Const operands get injected directly into the
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// template. Note that we don't need to escape $
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// here unlike normal inline assembly.
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template_str.push_str(string);
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}
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}
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}
|
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}
|
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}
|
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if intel_syntax {
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template_str.push_str("\n.att_syntax\n");
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}
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unsafe {
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llvm::LLVMRustAppendModuleInlineAsm(
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self.llmod,
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template_str.as_ptr().cast(),
|
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template_str.len(),
|
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);
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}
|
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}
|
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}
|
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|
|
pub(crate) fn inline_asm_call(
|
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bx: &mut Builder<'a, 'll, 'tcx>,
|
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asm: &str,
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cons: &str,
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inputs: &[&'ll Value],
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output: &'ll llvm::Type,
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volatile: bool,
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alignstack: bool,
|
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dia: LlvmAsmDialect,
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line_spans: &[Span],
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) -> Option<&'ll Value> {
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let volatile = if volatile { llvm::True } else { llvm::False };
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let alignstack = if alignstack { llvm::True } else { llvm::False };
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let argtys = inputs
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.iter()
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.map(|v| {
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debug!("Asm Input Type: {:?}", *v);
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bx.cx.val_ty(*v)
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})
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.collect::<Vec<_>>();
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|
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debug!("Asm Output Type: {:?}", output);
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let fty = bx.cx.type_func(&argtys[..], output);
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unsafe {
|
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// Ask LLVM to verify that the constraints are well-formed.
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let constraints_ok = llvm::LLVMRustInlineAsmVerify(fty, cons.as_ptr().cast(), cons.len());
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debug!("constraint verification result: {:?}", constraints_ok);
|
|
if constraints_ok {
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let v = llvm::LLVMRustInlineAsm(
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fty,
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asm.as_ptr().cast(),
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asm.len(),
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cons.as_ptr().cast(),
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cons.len(),
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volatile,
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alignstack,
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llvm::AsmDialect::from_generic(dia),
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);
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let call = bx.call(fty, v, inputs, None);
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|
|
// Store mark in a metadata node so we can map LLVM errors
|
|
// back to source locations. See #17552.
|
|
let key = "srcloc";
|
|
let kind = llvm::LLVMGetMDKindIDInContext(
|
|
bx.llcx,
|
|
key.as_ptr() as *const c_char,
|
|
key.len() as c_uint,
|
|
);
|
|
|
|
// srcloc contains one integer for each line of assembly code.
|
|
// Unfortunately this isn't enough to encode a full span so instead
|
|
// we just encode the start position of each line.
|
|
// FIXME: Figure out a way to pass the entire line spans.
|
|
let mut srcloc = vec![];
|
|
if dia == LlvmAsmDialect::Intel && line_spans.len() > 1 {
|
|
// LLVM inserts an extra line to add the ".intel_syntax", so add
|
|
// a dummy srcloc entry for it.
|
|
//
|
|
// Don't do this if we only have 1 line span since that may be
|
|
// due to the asm template string coming from a macro. LLVM will
|
|
// default to the first srcloc for lines that don't have an
|
|
// associated srcloc.
|
|
srcloc.push(bx.const_i32(0));
|
|
}
|
|
srcloc.extend(line_spans.iter().map(|span| bx.const_i32(span.lo().to_u32() as i32)));
|
|
let md = llvm::LLVMMDNodeInContext(bx.llcx, srcloc.as_ptr(), srcloc.len() as u32);
|
|
llvm::LLVMSetMetadata(call, kind, md);
|
|
|
|
Some(call)
|
|
} else {
|
|
// LLVM has detected an issue with our constraints, bail out
|
|
None
|
|
}
|
|
}
|
|
}
|
|
|
|
/// If the register is an xmm/ymm/zmm register then return its index.
|
|
fn xmm_reg_index(reg: InlineAsmReg) -> Option<u32> {
|
|
match reg {
|
|
InlineAsmReg::X86(reg)
|
|
if reg as u32 >= X86InlineAsmReg::xmm0 as u32
|
|
&& reg as u32 <= X86InlineAsmReg::xmm15 as u32 =>
|
|
{
|
|
Some(reg as u32 - X86InlineAsmReg::xmm0 as u32)
|
|
}
|
|
InlineAsmReg::X86(reg)
|
|
if reg as u32 >= X86InlineAsmReg::ymm0 as u32
|
|
&& reg as u32 <= X86InlineAsmReg::ymm15 as u32 =>
|
|
{
|
|
Some(reg as u32 - X86InlineAsmReg::ymm0 as u32)
|
|
}
|
|
InlineAsmReg::X86(reg)
|
|
if reg as u32 >= X86InlineAsmReg::zmm0 as u32
|
|
&& reg as u32 <= X86InlineAsmReg::zmm31 as u32 =>
|
|
{
|
|
Some(reg as u32 - X86InlineAsmReg::zmm0 as u32)
|
|
}
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
/// If the register is an AArch64 vector register then return its index.
|
|
fn a64_vreg_index(reg: InlineAsmReg) -> Option<u32> {
|
|
match reg {
|
|
InlineAsmReg::AArch64(reg)
|
|
if reg as u32 >= AArch64InlineAsmReg::v0 as u32
|
|
&& reg as u32 <= AArch64InlineAsmReg::v31 as u32 =>
|
|
{
|
|
Some(reg as u32 - AArch64InlineAsmReg::v0 as u32)
|
|
}
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
/// Converts a register class to an LLVM constraint code.
|
|
fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>) -> String {
|
|
match reg {
|
|
// For vector registers LLVM wants the register name to match the type size.
|
|
InlineAsmRegOrRegClass::Reg(reg) => {
|
|
if let Some(idx) = xmm_reg_index(reg) {
|
|
let class = if let Some(layout) = layout {
|
|
match layout.size.bytes() {
|
|
64 => 'z',
|
|
32 => 'y',
|
|
_ => 'x',
|
|
}
|
|
} else {
|
|
// We use f32 as the type for discarded outputs
|
|
'x'
|
|
};
|
|
format!("{{{}mm{}}}", class, idx)
|
|
} else if let Some(idx) = a64_vreg_index(reg) {
|
|
let class = if let Some(layout) = layout {
|
|
match layout.size.bytes() {
|
|
16 => 'q',
|
|
8 => 'd',
|
|
4 => 's',
|
|
2 => 'h',
|
|
1 => 'd', // We fixup i8 to i8x8
|
|
_ => unreachable!(),
|
|
}
|
|
} else {
|
|
// We use i64x2 as the type for discarded outputs
|
|
'q'
|
|
};
|
|
format!("{{{}{}}}", class, idx)
|
|
} else if reg == InlineAsmReg::AArch64(AArch64InlineAsmReg::x30) {
|
|
// LLVM doesn't recognize x30
|
|
"{lr}".to_string()
|
|
} else if reg == InlineAsmReg::Arm(ArmInlineAsmReg::r14) {
|
|
// LLVM doesn't recognize r14
|
|
"{lr}".to_string()
|
|
} else {
|
|
format!("{{{}}}", reg.name())
|
|
}
|
|
}
|
|
InlineAsmRegOrRegClass::RegClass(reg) => match reg {
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => "w",
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x",
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => "l",
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => "t",
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
|
|
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
|
|
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => "Q",
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => "q",
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
|
|
InlineAsmRegClass::X86(
|
|
X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg,
|
|
) => unreachable!("clobber-only"),
|
|
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
|
|
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
|
|
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => "r",
|
|
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => "f",
|
|
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
|
|
bug!("LLVM backend does not support SPIR-V")
|
|
}
|
|
InlineAsmRegClass::Err => unreachable!(),
|
|
}
|
|
.to_string(),
|
|
}
|
|
}
|
|
|
|
/// Converts a modifier into LLVM's equivalent modifier.
|
|
fn modifier_to_llvm(
|
|
arch: InlineAsmArch,
|
|
reg: InlineAsmRegClass,
|
|
modifier: Option<char>,
|
|
) -> Option<char> {
|
|
match reg {
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => modifier,
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
|
|
| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
|
|
if modifier == Some('v') { None } else { modifier }
|
|
}
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => None,
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => Some('P'),
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
|
|
if modifier.is_none() {
|
|
Some('q')
|
|
} else {
|
|
modifier
|
|
}
|
|
}
|
|
InlineAsmRegClass::Hexagon(_) => None,
|
|
InlineAsmRegClass::Mips(_) => None,
|
|
InlineAsmRegClass::Nvptx(_) => None,
|
|
InlineAsmRegClass::PowerPC(_) => None,
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
|
|
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => match modifier {
|
|
None if arch == InlineAsmArch::X86_64 => Some('q'),
|
|
None => Some('k'),
|
|
Some('l') => Some('b'),
|
|
Some('h') => Some('h'),
|
|
Some('x') => Some('w'),
|
|
Some('e') => Some('k'),
|
|
Some('r') => Some('q'),
|
|
_ => unreachable!(),
|
|
},
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => None,
|
|
InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::xmm_reg)
|
|
| InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::ymm_reg)
|
|
| InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::zmm_reg) => match (reg, modifier) {
|
|
(X86InlineAsmRegClass::xmm_reg, None) => Some('x'),
|
|
(X86InlineAsmRegClass::ymm_reg, None) => Some('t'),
|
|
(X86InlineAsmRegClass::zmm_reg, None) => Some('g'),
|
|
(_, Some('x')) => Some('x'),
|
|
(_, Some('y')) => Some('t'),
|
|
(_, Some('z')) => Some('g'),
|
|
_ => unreachable!(),
|
|
},
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None,
|
|
InlineAsmRegClass::Bpf(_) => None,
|
|
InlineAsmRegClass::S390x(_) => None,
|
|
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
|
|
bug!("LLVM backend does not support SPIR-V")
|
|
}
|
|
InlineAsmRegClass::Err => unreachable!(),
|
|
}
|
|
}
|
|
|
|
/// Type to use for outputs that are discarded. It doesn't really matter what
|
|
/// the type is, as long as it is valid for the constraint code.
|
|
fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll Type {
|
|
match reg {
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => cx.type_i32(),
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
|
|
| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
|
|
cx.type_vector(cx.type_i64(), 2)
|
|
}
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => cx.type_i32(),
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => cx.type_f64(),
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
|
|
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
|
|
cx.type_vector(cx.type_i64(), 2)
|
|
}
|
|
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
|
|
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
|
|
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
|
|
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
|
|
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
|
|
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => cx.type_i32(),
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => cx.type_i8(),
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
|
|
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg) => {
|
|
unreachable!("clobber-only")
|
|
}
|
|
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
|
|
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
|
|
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
|
|
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => cx.type_i32(),
|
|
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => cx.type_f64(),
|
|
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
|
|
bug!("LLVM backend does not support SPIR-V")
|
|
}
|
|
InlineAsmRegClass::Err => unreachable!(),
|
|
}
|
|
}
|
|
|
|
/// Helper function to get the LLVM type for a Scalar. Pointers are returned as
|
|
/// the equivalent integer type.
|
|
fn llvm_asm_scalar_type(cx: &CodegenCx<'ll, 'tcx>, scalar: Scalar) -> &'ll Type {
|
|
match scalar.value {
|
|
Primitive::Int(Integer::I8, _) => cx.type_i8(),
|
|
Primitive::Int(Integer::I16, _) => cx.type_i16(),
|
|
Primitive::Int(Integer::I32, _) => cx.type_i32(),
|
|
Primitive::Int(Integer::I64, _) => cx.type_i64(),
|
|
Primitive::F32 => cx.type_f32(),
|
|
Primitive::F64 => cx.type_f64(),
|
|
Primitive::Pointer => cx.type_isize(),
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
|
|
/// Fix up an input value to work around LLVM bugs.
|
|
fn llvm_fixup_input(
|
|
bx: &mut Builder<'a, 'll, 'tcx>,
|
|
mut value: &'ll Value,
|
|
reg: InlineAsmRegClass,
|
|
layout: &TyAndLayout<'tcx>,
|
|
) -> &'ll Value {
|
|
match (reg, layout.abi) {
|
|
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
|
|
if let Primitive::Int(Integer::I8, _) = s.value {
|
|
let vec_ty = bx.cx.type_vector(bx.cx.type_i8(), 8);
|
|
bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
|
|
} else {
|
|
value
|
|
}
|
|
}
|
|
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
|
|
let elem_ty = llvm_asm_scalar_type(bx.cx, s);
|
|
let count = 16 / layout.size.bytes();
|
|
let vec_ty = bx.cx.type_vector(elem_ty, count);
|
|
if let Primitive::Pointer = s.value {
|
|
value = bx.ptrtoint(value, bx.cx.type_isize());
|
|
}
|
|
bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
|
|
}
|
|
(
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
|
|
Abi::Vector { element, count },
|
|
) if layout.size.bytes() == 8 => {
|
|
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
|
|
let vec_ty = bx.cx.type_vector(elem_ty, count);
|
|
let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
|
|
bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
|
|
}
|
|
(InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
|
|
if s.value == Primitive::F64 =>
|
|
{
|
|
bx.bitcast(value, bx.cx.type_i64())
|
|
}
|
|
(
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
|
|
Abi::Vector { .. },
|
|
) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
|
|
(
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
|
|
Abi::Scalar(s),
|
|
) => {
|
|
if let Primitive::Int(Integer::I32, _) = s.value {
|
|
bx.bitcast(value, bx.cx.type_f32())
|
|
} else {
|
|
value
|
|
}
|
|
}
|
|
(
|
|
InlineAsmRegClass::Arm(
|
|
ArmInlineAsmRegClass::dreg
|
|
| ArmInlineAsmRegClass::dreg_low8
|
|
| ArmInlineAsmRegClass::dreg_low16,
|
|
),
|
|
Abi::Scalar(s),
|
|
) => {
|
|
if let Primitive::Int(Integer::I64, _) = s.value {
|
|
bx.bitcast(value, bx.cx.type_f64())
|
|
} else {
|
|
value
|
|
}
|
|
}
|
|
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
|
|
// MIPS only supports register-length arithmetics.
|
|
Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
|
|
Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
|
|
Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
|
|
_ => value,
|
|
},
|
|
_ => value,
|
|
}
|
|
}
|
|
|
|
/// Fix up an output value to work around LLVM bugs.
|
|
fn llvm_fixup_output(
|
|
bx: &mut Builder<'a, 'll, 'tcx>,
|
|
mut value: &'ll Value,
|
|
reg: InlineAsmRegClass,
|
|
layout: &TyAndLayout<'tcx>,
|
|
) -> &'ll Value {
|
|
match (reg, layout.abi) {
|
|
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
|
|
if let Primitive::Int(Integer::I8, _) = s.value {
|
|
bx.extract_element(value, bx.const_i32(0))
|
|
} else {
|
|
value
|
|
}
|
|
}
|
|
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
|
|
value = bx.extract_element(value, bx.const_i32(0));
|
|
if let Primitive::Pointer = s.value {
|
|
value = bx.inttoptr(value, layout.llvm_type(bx.cx));
|
|
}
|
|
value
|
|
}
|
|
(
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
|
|
Abi::Vector { element, count },
|
|
) if layout.size.bytes() == 8 => {
|
|
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
|
|
let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
|
|
let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
|
|
bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
|
|
}
|
|
(InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
|
|
if s.value == Primitive::F64 =>
|
|
{
|
|
bx.bitcast(value, bx.cx.type_f64())
|
|
}
|
|
(
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
|
|
Abi::Vector { .. },
|
|
) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
|
|
(
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
|
|
Abi::Scalar(s),
|
|
) => {
|
|
if let Primitive::Int(Integer::I32, _) = s.value {
|
|
bx.bitcast(value, bx.cx.type_i32())
|
|
} else {
|
|
value
|
|
}
|
|
}
|
|
(
|
|
InlineAsmRegClass::Arm(
|
|
ArmInlineAsmRegClass::dreg
|
|
| ArmInlineAsmRegClass::dreg_low8
|
|
| ArmInlineAsmRegClass::dreg_low16,
|
|
),
|
|
Abi::Scalar(s),
|
|
) => {
|
|
if let Primitive::Int(Integer::I64, _) = s.value {
|
|
bx.bitcast(value, bx.cx.type_i64())
|
|
} else {
|
|
value
|
|
}
|
|
}
|
|
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
|
|
// MIPS only supports register-length arithmetics.
|
|
Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
|
|
Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
|
|
Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
|
|
Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
|
|
_ => value,
|
|
},
|
|
_ => value,
|
|
}
|
|
}
|
|
|
|
/// Output type to use for llvm_fixup_output.
|
|
fn llvm_fixup_output_type(
|
|
cx: &CodegenCx<'ll, 'tcx>,
|
|
reg: InlineAsmRegClass,
|
|
layout: &TyAndLayout<'tcx>,
|
|
) -> &'ll Type {
|
|
match (reg, layout.abi) {
|
|
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
|
|
if let Primitive::Int(Integer::I8, _) = s.value {
|
|
cx.type_vector(cx.type_i8(), 8)
|
|
} else {
|
|
layout.llvm_type(cx)
|
|
}
|
|
}
|
|
(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
|
|
let elem_ty = llvm_asm_scalar_type(cx, s);
|
|
let count = 16 / layout.size.bytes();
|
|
cx.type_vector(elem_ty, count)
|
|
}
|
|
(
|
|
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
|
|
Abi::Vector { element, count },
|
|
) if layout.size.bytes() == 8 => {
|
|
let elem_ty = llvm_asm_scalar_type(cx, element);
|
|
cx.type_vector(elem_ty, count * 2)
|
|
}
|
|
(InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
|
|
if s.value == Primitive::F64 =>
|
|
{
|
|
cx.type_i64()
|
|
}
|
|
(
|
|
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
|
|
Abi::Vector { .. },
|
|
) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
|
|
(
|
|
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
|
|
Abi::Scalar(s),
|
|
) => {
|
|
if let Primitive::Int(Integer::I32, _) = s.value {
|
|
cx.type_f32()
|
|
} else {
|
|
layout.llvm_type(cx)
|
|
}
|
|
}
|
|
(
|
|
InlineAsmRegClass::Arm(
|
|
ArmInlineAsmRegClass::dreg
|
|
| ArmInlineAsmRegClass::dreg_low8
|
|
| ArmInlineAsmRegClass::dreg_low16,
|
|
),
|
|
Abi::Scalar(s),
|
|
) => {
|
|
if let Primitive::Int(Integer::I64, _) = s.value {
|
|
cx.type_f64()
|
|
} else {
|
|
layout.llvm_type(cx)
|
|
}
|
|
}
|
|
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
|
|
// MIPS only supports register-length arithmetics.
|
|
Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
|
|
Primitive::F32 => cx.type_i32(),
|
|
Primitive::F64 => cx.type_i64(),
|
|
_ => layout.llvm_type(cx),
|
|
},
|
|
_ => layout.llvm_type(cx),
|
|
}
|
|
}
|