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Add new Tier-3 target: riscv64a23-unknown-linux-gnu MCP: [Tier 3 target proposal: riscv64a23-unknown-linux-gnu](https://github.com/rust-lang/compiler-team/issues/894) Changes: - add new target: riscv64a23-unknown-linux-gnu - add target page
475 lines
5.0 KiB
Plaintext
475 lines
5.0 KiB
Plaintext
warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`
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--> $DIR/target_feature.rs:16:10
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LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
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| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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= note: expected values for `target_feature` are: `10e60`
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`2e3`
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`32s`
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`3e3r1`
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`3e3r2`
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`3e3r3`
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`3e7`
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`7e10`
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`a`
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`aclass`
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`adx`
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`aes`
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`altivec`
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`alu32`
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`amx-avx512`
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`amx-bf16`
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`amx-complex`
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`amx-fp16`
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`amx-fp8`
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`amx-int8`
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`amx-movrs`
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`amx-tf32`
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`amx-tile`
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`amx-transpose`
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`apxf`
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`atomics`
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`avx`
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`avx10.1`
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`avx10.2`
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`avx2`
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`avx512bf16`
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`avx512bitalg`
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`avx512bw`
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`avx512cd`
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`avx512dq`
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`avx512f`
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`avx512fp16`
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`avx512ifma`
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`avx512vbmi`
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`avx512vbmi2`
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`avx512vl`
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`avx512vnni`
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`avx512vp2intersect`
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`avx512vpopcntdq`
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`avxifma`
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`avxneconvert`
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`avxvnni`
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`avxvnniint16`
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`avxvnniint8`
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`b`
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`backchain`
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`bf16`
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`bmi1`
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`bmi2`
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`bti`
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`bulk-memory`
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`c`
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`cache`
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`cmpxchg16b`
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`concurrent-functions`
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`crc`
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`crt-static`
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`cssc`
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`d`
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`d32`
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`deflate-conversion`
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`dit`
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`div32`
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`doloop`
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`dotprod`
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`dpb`
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`dpb2`
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`dsp`
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`dsp1e2`
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`dspe60`
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`e`
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`e1`
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`e2`
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`ecv`
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`edsp`
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`elrw`
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`enhanced-sort`
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`ermsb`
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`exception-handling`
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`extended-const`
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`f`
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`f16c`
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`f32mm`
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`f64mm`
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`faminmax`
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`fcma`
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`fdivdu`
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`fhm`
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`flagm`
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`flagm2`
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`float1e2`
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`float1e3`
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`float3e4`
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`float7e60`
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`floate1`
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`fma`
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`fp-armv8`
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`fp16`
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`fp64`
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`fp8`
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`fp8dot2`
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`fp8dot4`
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`fp8fma`
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`fpregs`
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`fpuv2_df`
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`fpuv2_sf`
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`fpuv3_df`
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`fpuv3_hf`
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`fpuv3_hi`
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`fpuv3_sf`
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`frecipe`
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`frintts`
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`fxsr`
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`gfni`
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`guarded-storage`
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`hard-float`
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`hard-float-abi`
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`hard-tp`
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`hbc`
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`high-registers`
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`high-word`
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`hvx`
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`hvx-length128b`
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`hwdiv`
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`i8mm`
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`isa-68000`
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`isa-68010`
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`isa-68020`
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`isa-68030`
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`isa-68040`
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`isa-68060`
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`isa-68881`
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`isa-68882`
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`jsconv`
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`kl`
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`lahfsahf`
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`lam-bh`
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`lamcas`
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`lasx`
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`lbt`
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`ld-seq-sa`
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`leoncasa`
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`lor`
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`lse`
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`lse128`
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`lse2`
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`lsx`
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`lut`
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`lvz`
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`lzcnt`
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`m`
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`mclass`
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`message-security-assist-extension12`
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`message-security-assist-extension3`
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`message-security-assist-extension4`
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`message-security-assist-extension5`
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`message-security-assist-extension8`
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`message-security-assist-extension9`
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`miscellaneous-extensions-2`
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`miscellaneous-extensions-3`
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`miscellaneous-extensions-4`
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`mops`
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`movbe`
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`movrs`
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`mp`
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`mp1e2`
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`msa`
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`msync`
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`mte`
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`multivalue`
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`mutable-globals`
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`neon`
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`nnp-assist`
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`nontrapping-fptoint`
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`nvic`
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`outline-atomics`
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`paca`
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`pacg`
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`pan`
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`partword-atomics`
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`pauth-lr`
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`pclmulqdq`
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`pmuv3`
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`popcnt`
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`power10-vector`
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`power8-altivec`
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`power8-crypto`
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`power8-vector`
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`power9-altivec`
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`power9-vector`
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`prfchw`
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`ptx32`
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`ptx40`
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`ptx41`
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`ptx42`
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`ptx43`
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`ptx50`
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`ptx60`
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`ptx61`
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`ptx62`
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`ptx63`
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`ptx64`
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`ptx65`
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`ptx70`
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`ptx71`
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`ptx72`
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`ptx73`
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`ptx74`
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`ptx75`
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`ptx76`
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`ptx77`
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`ptx78`
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`ptx80`
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`ptx81`
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`ptx82`
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`ptx83`
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`ptx84`
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`ptx85`
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`ptx86`
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`ptx87`
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`quadword-atomics`
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`rand`
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`ras`
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`rclass`
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`rcpc`
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`rcpc2`
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`rcpc3`
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`rdm`
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`rdrand`
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`rdseed`
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`reference-types`
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`relax`
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`relaxed-simd`
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`rtm`
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`rva23u64`
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`sb`
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`scq`
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`sha`
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`sha2`
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`sha3`
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`sha512`
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`sign-ext`
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`simd128`
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`sm3`
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`sm4`
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`sm_100`
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`sm_100a`
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`sm_101`
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`sm_101a`
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`sm_120`
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`sm_120a`
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`sm_20`
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`sm_21`
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`sm_30`
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`sm_32`
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`sm_35`
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`sm_37`
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`sm_50`
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`sm_52`
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`sm_53`
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`sm_60`
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`sm_61`
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`sm_62`
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`sm_70`
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`sm_72`
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`sm_75`
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`sm_80`
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`sm_86`
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`sm_87`
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`sm_89`
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`sm_90`
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`sm_90a`
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`sme`
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`sme-b16b16`
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`sme-f16f16`
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`sme-f64f64`
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`sme-f8f16`
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`sme-f8f32`
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`sme-fa64`
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`sme-i16i64`
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`sme-lutv2`
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`sme2`
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`sme2p1`
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`soft-float`
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`spe`
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`ssbs`
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`sse`
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`sse2`
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`sse3`
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`sse4.1`
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`sse4.2`
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`sse4a`
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`ssse3`
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`ssve-fp8dot2`
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`ssve-fp8dot4`
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`ssve-fp8fma`
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`supm`
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`sve`
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`sve-b16b16`
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`sve2`
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`sve2-aes`
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`sve2-bitperm`
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`sve2-sha3`
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`sve2-sm4`
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`sve2p1`
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`tail-call`
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`tbm`
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`thumb-mode`
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`thumb2`
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`tme`
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`transactional-execution`
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`trust`
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`trustzone`
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`ual`
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`unaligned-scalar-mem`
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`unaligned-vector-mem`
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`v`
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`v5te`
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`v6`
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`v6k`
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`v6t2`
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`v7`
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`v8`
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`v8.1a`
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`v8.2a`
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`v8.3a`
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`v8.4a`
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`v8.5a`
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`v8.6a`
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`v8.7a`
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`v8.8a`
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`v8.9a`
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`v8plus`
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`v9`
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`v9.1a`
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`v9.2a`
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`v9.3a`
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`v9.4a`
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`v9.5a`
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`v9a`
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`vaes`
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`vdsp2e60f`
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`vdspv1`
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`vdspv2`
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`vector`
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`vector-enhancements-1`
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`vector-enhancements-2`
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`vector-enhancements-3`
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`vector-packed-decimal`
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`vector-packed-decimal-enhancement`
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`vector-packed-decimal-enhancement-2`
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`vector-packed-decimal-enhancement-3`
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`vfp2`
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`vfp3`
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`vfp4`
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`vh`
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`virt`
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`virtualization`
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`vpclmulqdq`
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`vsx`
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`wfxt`
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`wide-arithmetic`
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`widekl`
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`x87`
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`xop`
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`xsave`
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`xsavec`
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`xsaveopt`
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`xsaves`
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`za128rs`
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`za64rs`
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`zaamo`
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`zabha`
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`zacas`
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`zalrsc`
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`zama16b`
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`zawrs`
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`zba`
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`zbb`
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`zbc`
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`zbkb`
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`zbkc`
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`zbkx`
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`zbs`
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`zca`
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`zcb`
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`zcmop`
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`zdinx`
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`zfa`
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`zfbfmin`
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`zfh`
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`zfhmin`
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`zfinx`
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`zhinx`
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`zhinxmin`
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`zic64b`
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`zicbom`
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`zicbop`
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`zicboz`
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`ziccamoa`
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`ziccif`
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`zicclsm`
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`ziccrse`
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`zicntr`
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`zicond`
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`zicsr`
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`zifencei`
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`zihintntl`
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`zihintpause`
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`zihpm`
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`zimop`
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`zk`
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`zkn`
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`zknd`
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`zkne`
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`zknh`
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`zkr`
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`zks`
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`zksed`
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`zksh`
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`zkt`
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`ztso`
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`zvbb`
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`zvbc`
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`zve32f`
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`zve32x`
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`zve64d`
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`zve64f`
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`zve64x`
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`zvfbfmin`
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`zvfbfwma`
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`zvfh`
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`zvfhmin`
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`zvkb`
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`zvkg`
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`zvkn`
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`zvknc`
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`zvkned`
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`zvkng`
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`zvknha`
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`zvknhb`
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`zvks`
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`zvksc`
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`zvksed`
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`zvksg`
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`zvksh`
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`zvkt`
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`zvl1024b`
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`zvl128b`
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`zvl16384b`
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`zvl2048b`
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`zvl256b`
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`zvl32768b`
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`zvl32b`
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`zvl4096b`
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`zvl512b`
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`zvl64b`
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`zvl65536b`, and `zvl8192b`
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= note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
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= note: `#[warn(unexpected_cfgs)]` on by default
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warning: 1 warning emitted
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