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limit CoreVoltage eum to values up to 1.30V, because we do not support unlocking higher voltages
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1-rafael-1
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133500167c
@ -140,6 +140,10 @@ pub enum PeriClkSrc {
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///
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/// The voltage regulator can be configured for different output voltages.
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/// Higher voltages allow for higher clock frequencies but increase power consumption and heat.
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///
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/// **Note**: For RP235x the maximum voltage is 1.30V, unless unlocked by setting unless the voltage limit
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/// is disabled using the disable_voltage_limit field in the vreg_ctrl register. For lack of practical use at this
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/// point in time, this is not implemented here. So the maximum voltage in this enum is 1.30V for now.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[repr(u8)]
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pub enum CoreVoltage {
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@ -227,54 +231,6 @@ pub enum CoreVoltage {
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.30V
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V1_30 = 0b01111,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.35V
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V1_35 = 0b10000,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.40V
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V1_40 = 0b10001,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.50V
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V1_50 = 0b10010,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.60V
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V1_60 = 0b10011,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.65V
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V1_65 = 0b10100,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.70V
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V1_70 = 0b10101,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.80V
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V1_80 = 0b10110,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 1.90V
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V1_90 = 0b10111,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 2.00V
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V2_00 = 0b11000,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 2.35V
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V2_35 = 0b11001,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 2.50V
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V2_50 = 0b11010,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 2.65V
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V2_65 = 0b11011,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 2.80V
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V2_80 = 0b11100,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 3.00V
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V3_00 = 0b11101,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 3.15V
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V3_15 = 0b11110,
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#[cfg(feature = "_rp235x")]
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/// RP235x: 3.30V
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V3_30 = 0b11111,
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}
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impl CoreVoltage {
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@ -313,13 +269,7 @@ impl CoreVoltage {
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CoreVoltage::V1_20 => 0b01010, // 0.903V (~75% of 1.20V)
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CoreVoltage::V1_25 => 0b01010, // 0.903V (~72% of 1.25V)
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CoreVoltage::V1_30 => 0b01011, // 0.946V (~73% of 1.30V)
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CoreVoltage::V1_35 => 0b01011, // 0.946V (~70% of 1.35V)
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CoreVoltage::V1_40 => 0b01100, // 0.989V (~71% of 1.40V)
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CoreVoltage::V1_50 => 0b01101, // 1.032V (~69% of 1.50V)
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CoreVoltage::V1_60 => 0b01110, // 1.075V (~67% of 1.60V)
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CoreVoltage::V1_65 => 0b01110, // 1.075V (~65% of 1.65V)
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CoreVoltage::V1_70 => 0b01111, // 1.118V (~66% of 1.70V)
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_ => 0b10000, // the rp2350 datasheet repeats this value for all other core voltages
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// all others: 0.946V (see CoreVoltage: we do not support setting Voltages higher than 1.30V at this point)
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}
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}
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}
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@ -1083,45 +1033,17 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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// If the target voltage is different from the current one, we need to change it
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if target_vsel != current_vsel {
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// Set the voltage regulator to the target voltage
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#[cfg(feature = "rp2040")]
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{
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// Use modify() to preserve the HIZ and EN bits - otherwise we will disable the regulator when changing voltage
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vreg.vreg().modify(|w| w.set_vsel(target_vsel));
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}
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vreg.vreg().modify(|w| w.set_vsel(target_vsel));
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#[cfg(feature = "_rp235x")]
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{
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// The rp235x has a different way of controlling the voltage regulator
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// Changes to the voltage regulator are protected by a password, see datasheet section 6.4
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// The password is "5AFE" (0x5AFE), it must be set in the top 16 bits of the register
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// The rp235x by default locks the voltage regulator control, so we need to unlock it first
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// See datasheet section 6.3.2. Software Control
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vreg.vreg_ctrl().modify(|w| {
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// Add password to top 16 bits, preserving the rest, repeat below for other registers
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w.0 = (w.0 & 0x0000FFFF) | (0x5AFE << 16);
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w.set_unlock(true);
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*w
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});
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// Set the voltage
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vreg.vreg().modify(|w| {
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w.0 = (w.0 & 0x0000FFFF) | (0x5AFE << 16);
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w.set_vsel(target_vsel);
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*w
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});
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// The rp235x has two more registers to set the voltage for low power mode
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vreg.vreg_lp_entry().modify(|w| {
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w.0 = (w.0 & 0x0000FFFF) | (0x5AFE << 16);
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w.set_vsel(target_vsel);
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*w
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});
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vreg.vreg_lp_exit().modify(|w| {
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w.0 = (w.0 & 0x0000FFFF) | (0x5AFE << 16);
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w.set_vsel(target_vsel);
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*w
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});
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}
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// For rp235x changes to the voltage regulator are protected by a password, see datasheet section 6.4 Power Management (POWMAN) Registers
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// The password is "5AFE" (0x5AFE), it must be set in the top 16 bits of the register
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vreg.vreg().modify(|w| {
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w.0 = (w.0 & 0x0000FFFF) | (0x5AFE << 16); // Set the password
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w.set_vsel(target_vsel);
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*w
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});
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// Wait for the voltage to stabilize. Use the provided delay or default based on voltage
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let settling_time_us = config.voltage_stabilization_delay_us.unwrap_or_else(|| {
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@ -1140,23 +1062,17 @@ pub(crate) unsafe fn init(config: ClockConfig) {
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}
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// Only now set the BOD level. At this point the voltage is considered stable.
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#[cfg(feature = "rp2040")]
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vreg.bod().write(|w| {
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w.set_vsel(voltage.recommended_bod());
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w.set_en(true); // Enable brownout detection
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});
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#[cfg(feature = "_rp235x")]
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{
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// The rp235x has a separate register for the BOD level in low power mode
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vreg.bod_lp_entry().write(|w| {
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w.set_vsel(voltage.recommended_bod());
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w.set_en(true); // Enable brownout detection
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});
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vreg.bod_lp_exit().write(|w| {
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w.set_vsel(voltage.recommended_bod());
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w.set_en(true); // Enable brownout detection
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});
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}
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vreg.bod().write(|w| {
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w.0 = (w.0 & 0x0000FFFF) | (0x5AFE << 16); // Set the password
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w.set_vsel(voltage.recommended_bod());
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w.set_en(true); // Enable brownout detection
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});
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}
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}
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@ -1527,23 +1443,8 @@ pub fn core_voltage() -> Result<CoreVoltage, &'static str> {
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0b01101 => Ok(CoreVoltage::V1_20),
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0b01110 => Ok(CoreVoltage::V1_25),
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0b01111 => Ok(CoreVoltage::V1_30),
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0b10000 => Ok(CoreVoltage::V1_35),
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0b10001 => Ok(CoreVoltage::V1_40),
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0b10010 => Ok(CoreVoltage::V1_50),
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0b10011 => Ok(CoreVoltage::V1_60),
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0b10100 => Ok(CoreVoltage::V1_65),
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0b10101 => Ok(CoreVoltage::V1_70),
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0b10110 => Ok(CoreVoltage::V1_80),
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0b10111 => Ok(CoreVoltage::V1_90),
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0b11000 => Ok(CoreVoltage::V2_00),
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0b11001 => Ok(CoreVoltage::V2_35),
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0b11010 => Ok(CoreVoltage::V2_50),
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0b11011 => Ok(CoreVoltage::V2_65),
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0b11100 => Ok(CoreVoltage::V2_80),
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0b11101 => Ok(CoreVoltage::V3_00),
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0b11110 => Ok(CoreVoltage::V3_15),
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0b11111 => Ok(CoreVoltage::V3_30),
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_ => Err("Unexpected value in register"),
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// see CoreVoltage: we do not support setting Voltages higher than 1.30V at this point
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}
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}
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}
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