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stm32/dac: fix dma pw size

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closes #2783
This commit is contained in:
xoviat
2026-04-08 19:46:44 -05:00
parent 1781e4a4d5
commit 32aaaa6fbb
3 changed files with 16 additions and 4 deletions
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6
embassy-stm32/src/dac/mod.rs
View File

@@ -333,13 +333,13 @@ impl<'d> DacChannel<'d, Async> {
// Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data {
ValueArray::Bit8(buf) => unsafe {
dma.write(buf, self.info.regs.dhr8r(self.idx).as_ptr() as *mut u8, tx_options)
dma.write_raw(buf, self.info.regs.dhr8r(self.idx).as_ptr() as *mut u32, tx_options)
},
ValueArray::Bit12Left(buf) => unsafe {
dma.write(buf, self.info.regs.dhr12l(self.idx).as_ptr() as *mut u16, tx_options)
dma.write_raw(buf, self.info.regs.dhr12l(self.idx).as_ptr() as *mut u32, tx_options)
},
ValueArray::Bit12Right(buf) => unsafe {
dma.write(buf, self.info.regs.dhr12r(self.idx).as_ptr() as *mut u16, tx_options)
dma.write_raw(buf, self.info.regs.dhr12r(self.idx).as_ptr() as *mut u32, tx_options)
},
};

12
tests/stm32/src/bin/dac.rs
View File

@@ -31,11 +31,21 @@ async fn main(_spawner: Spawner) {
let mut adc_pin = unsafe { core::ptr::read(&dac_pin) };
let mut dac = DacChannel::new_blocking(dac, dac_pin);
#[cfg(not(feature = "stm32g491re"))]
let mut adc = Adc::new(adc);
#[cfg(feature = "stm32g491re")]
let mut adc = Adc::new(adc, Default::default());
#[cfg(feature = "stm32h755zi")]
let normalization_factor = 256;
#[cfg(any(feature = "stm32f429zi", feature = "stm32f446re", feature = "stm32g071rb"))]
#[cfg(any(
feature = "stm32f429zi",
feature = "stm32f446re",
feature = "stm32g071rb",
feature = "stm32g491re"
))]
let normalization_factor: i32 = 16;
dac.set(Value::Bit8(0));

2
tests/stm32/src/common.rs
View File

@@ -128,6 +128,7 @@ define_peris!(
define_peris!(
UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
ADC = ADC2, DAC = DAC1, DAC_PIN = PA4,
@irq UART = {
USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;
DMA1_CHANNEL1 => embassy_stm32::dma::InterruptHandler<embassy_stm32::peripherals::DMA1_CH1>;
@@ -663,6 +664,7 @@ pub fn config() -> Config {
divq: Some(PllQDiv::DIV8), // 42.5 Mhz for fdcan.
divr: Some(PllRDiv::DIV2), // Main system clock at 170 MHz
});
config.rcc.mux.adc12sel = mux::Adcsel::SYS;
config.rcc.mux.fdcansel = mux::Fdcansel::PLL1_Q;
config.rcc.sys = Sysclk::PLL1_R;
}