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Merge pull request #3661 from esden/fix-ospi-n-qspi-command-naming-convention

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stm32/(o|q)spi: command naming convention fix
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Dario Nieuwenhuis 2024-12-17 23:04:31 +00:00 committed by GitHub
commit 341036a8b8
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4 changed files with 7 additions and 7 deletions
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2
embassy-stm32/src/ospi/mod.rs
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@ -520,7 +520,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
} }
/// Function used to control or configure the target device without data transfer /// Function used to control or configure the target device without data transfer
pub async fn command(&mut self, command: &TransferConfig) -> Result<(), OspiError> { pub fn blocking_command(&mut self, command: &TransferConfig) -> Result<(), OspiError> {
// Wait for peripheral to be free // Wait for peripheral to be free
while T::REGS.sr().read().busy() {} while T::REGS.sr().read().busy() {}

2
embassy-stm32/src/qspi/mod.rs
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@ -148,7 +148,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
} }
/// Do a QSPI command. /// Do a QSPI command.
pub fn command(&mut self, transaction: TransferConfig) { pub fn blocking_command(&mut self, transaction: TransferConfig) {
#[cfg(not(stm32h7))] #[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(false)); T::REGS.cr().modify(|v| v.set_dmaen(false));
self.setup_transaction(QspiMode::IndirectWrite, &transaction, None); self.setup_transaction(QspiMode::IndirectWrite, &transaction, None);

4
examples/stm32f7/src/bin/qspi.rs
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@ -72,7 +72,7 @@ impl<I: Instance> FlashMemory<I> {
address: None, address: None,
dummy: DummyCycles::_0, dummy: DummyCycles::_0,
}; };
self.qspi.command(transaction); self.qspi.blocking_command(transaction);
} }
pub fn reset_memory(&mut self) { pub fn reset_memory(&mut self) {
@ -143,7 +143,7 @@ impl<I: Instance> FlashMemory<I> {
dummy: DummyCycles::_0, dummy: DummyCycles::_0,
}; };
self.enable_write(); self.enable_write();
self.qspi.command(transaction); self.qspi.blocking_command(transaction);
self.wait_write_finish(); self.wait_write_finish();
} }

6
examples/stm32h7b0/src/bin/ospi_memory_mapped.rs
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@ -223,7 +223,7 @@ impl<I: Instance> FlashMemory<I> {
dummy: DummyCycles::_0, dummy: DummyCycles::_0,
..Default::default() ..Default::default()
}; };
self.ospi.command(&transaction).await.unwrap(); self.ospi.blocking_command(&transaction).unwrap();
} }
async fn exec_command(&mut self, cmd: u8) { async fn exec_command(&mut self, cmd: u8) {
@ -238,7 +238,7 @@ impl<I: Instance> FlashMemory<I> {
..Default::default() ..Default::default()
}; };
// info!("Excuting command: {:x}", transaction.instruction); // info!("Excuting command: {:x}", transaction.instruction);
self.ospi.command(&transaction).await.unwrap(); self.ospi.blocking_command(&transaction).unwrap();
} }
pub async fn reset_memory(&mut self) { pub async fn reset_memory(&mut self) {
@ -318,7 +318,7 @@ impl<I: Instance> FlashMemory<I> {
..Default::default() ..Default::default()
}; };
self.enable_write().await; self.enable_write().await;
self.ospi.command(&transaction).await.unwrap(); self.ospi.blocking_command(&transaction).unwrap();
self.wait_write_finish(); self.wait_write_finish();
} }