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Add #[allow(dead_code] attributes and rename spawner variable

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ragarnoy 2025-05-10 02:34:33 +02:00
parent cf60b11066
commit 65f67694a9
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1 changed files with 3 additions and 1 deletions
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4
examples/stm32h755cm7/src/bin/intercore.rs
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@ -48,6 +48,7 @@ mod shared {
/// Get LED state using safe bit operations /// Get LED state using safe bit operations
#[inline(never)] #[inline(never)]
#[allow(dead_code)]
pub fn get_led(&self, is_green: bool) -> bool { pub fn get_led(&self, is_green: bool) -> bool {
let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT };
@ -69,6 +70,7 @@ mod shared {
/// Get counter without incrementing /// Get counter without incrementing
#[inline(never)] #[inline(never)]
#[allow(dead_code)]
pub fn get_counter(&self) -> u32 { pub fn get_counter(&self) -> u32 {
let value = self.counter.load(Ordering::SeqCst); let value = self.counter.load(Ordering::SeqCst);
core::sync::atomic::compiler_fence(Ordering::SeqCst); core::sync::atomic::compiler_fence(Ordering::SeqCst);
@ -144,7 +146,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
} }
#[embassy_executor::main] #[embassy_executor::main]
async fn main(spawner: Spawner) -> ! { async fn main(_spawner: Spawner) -> ! {
// Configure MPU to make SRAM4 non-cacheable // Configure MPU to make SRAM4 non-cacheable
{ {
let mut cp = cortex_m::Peripherals::take().unwrap(); let mut cp = cortex_m::Peripherals::take().unwrap();