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stm32/usart: sending break character

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This commit is contained in:
Daniel Trnka 2024-08-21 13:15:48 +02:00
parent 1ff1f00d5a
commit bea1f34440
1 changed files with 20 additions and 0 deletions
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20
embassy-stm32/src/usart/mod.rs
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@ -520,6 +520,21 @@ impl<'d, M: Mode> UartTx<'d, M> {
pub fn blocking_flush(&mut self) -> Result<(), Error> { pub fn blocking_flush(&mut self) -> Result<(), Error> {
blocking_flush(self.info) blocking_flush(self.info)
} }
/// Send break character
pub fn send_break(&self) {
// Busy wait until previous break has been sent
#[cfg(any(usart_v1, usart_v2))]
while self.info.regs.cr1().read().sbk() {}
#[cfg(any(usart_v3, usart_v4))]
while self.info.regs.isr().read().sbkf() {}
// Send break right after completing the current character transmission
#[cfg(any(usart_v1, usart_v2))]
self.info.regs.cr1().modify(|w| w.set_sbk(true));
#[cfg(any(usart_v3, usart_v4))]
self.info.regs.rqr().write(|w| w.set_sbkrq(true));
}
} }
fn blocking_flush(info: &Info) -> Result<(), Error> { fn blocking_flush(info: &Info) -> Result<(), Error> {
@ -1365,6 +1380,11 @@ impl<'d, M: Mode> Uart<'d, M> {
pub fn split(self) -> (UartTx<'d, M>, UartRx<'d, M>) { pub fn split(self) -> (UartTx<'d, M>, UartRx<'d, M>) {
(self.tx, self.rx) (self.tx, self.rx)
} }
/// Send break character
pub fn send_break(&self) {
self.tx.send_break();
}
} }
fn reconfigure(info: &Info, kernel_clock: Hertz, config: &Config) -> Result<(), ConfigError> { fn reconfigure(info: &Info, kernel_clock: Hertz, config: &Config) -> Result<(), ConfigError> {