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Revert some hacky changes

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This commit is contained in:
James Munns
2026-03-10 16:15:46 +01:00
parent 8a19259bba
commit db3f3d1a8d
3 changed files with 21 additions and 50 deletions
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30
embassy-mcxa/src/clocks/operator.rs
View File

@@ -454,8 +454,6 @@ impl ClockOperator<'_> {
CoarseAmpGain, ExtalCapSel, InitTrim, ModeEn, StatusaLdoRdy, StatusaOscRdy, SupplyDet, XtalCapSel,
};
defmt::info!("prelock");
// Unlock the control first
self.vbat0.ldolcka().modify(|w| w.set_lock(false));
@@ -468,11 +466,6 @@ impl ClockOperator<'_> {
return Ok(());
};
// TODO: Why does the SDK do this?
self.ensure_ldo_active("osc32k", &PoweredClock::NormalEnabledDeepSleepDisabled)?;
defmt::info!("prebat");
// To enable and lock the LDO and bandgap:
//
// NOTE(AJM): "The FRO16K must be enabled before enabling the SRAM LDO or the bandgap"
@@ -491,14 +484,12 @@ impl ClockOperator<'_> {
w.set_bg_en(true);
});
defmt::info!("Preldo");
// 3. Wait for STATUSA[LDO_RDY] to become 1.
while self.vbat0.statusa().read().ldo_rdy() != StatusaLdoRdy::SET {}
// 4. Write 1h to LDOLCKA[LOCK].
self.vbat0.ldolcka().modify(|w| w.set_lock(true));
defmt::info!("prematch");
match &cfg.mode {
Osc32KMode::HighPower {
coarse_amp_gain,
@@ -511,8 +502,6 @@ impl ClockOperator<'_> {
// required based on the external crystal component ESR and CL values, and by the PCB parasitics on the EXTAL32K and
// XTAL32K pins. Configure 0h to OSCCTLA[MODE_EN], 1h to OSCCTLA[CAP_SEL_EN], and 1h to OSCCTLA[OSC_EN].
// * NOTE(AJM): You must write 1 to this field and OSCCTLA[OSC_EN] simultaneously.
use nxp_pac::scg::vals::Roscvld;
self.vbat0.oscctla().modify(|w| {
w.set_xtal_cap_sel(match xtal_cap_sel {
Osc32KCapSel::Cap2PicoF => XtalCapSel::SEL2,
@@ -566,10 +555,10 @@ impl ClockOperator<'_> {
self.vbat0.osclcka().modify(|w| w.set_lock(true));
// 4. Write 0h to OSCCTLA[EXTAL_CAP_SEL] and 0h to OSCCTLA[XTAL_CAP_SEL].
// self.vbat0.oscctla().modify(|w| {
// w.set_xtal_cap_sel(XtalCapSel::SEL0);
// w.set_extal_cap_sel(ExtalCapSel::SEL0);
// });
self.vbat0.oscctla().modify(|w| {
w.set_xtal_cap_sel(XtalCapSel::SEL0);
w.set_extal_cap_sel(ExtalCapSel::SEL0);
});
// 5. Alter OSCCLKE[CLKE] to clock gate different OSC32K outputs to different peripherals to reduce power consumption.
const ENABLED: Option<Clock> = Some(Clock {
@@ -592,17 +581,6 @@ impl ClockOperator<'_> {
}
w.set_clke(val);
});
self.scg0.rosccsr().write(|w| {
w.set_roscerr(nxp_pac::scg::vals::Roscerr::ENABLED_AND_ERROR);
});
self.scg0.rosccsr().modify(|w| {
w.set_lk(nxp_pac::scg::vals::RosccsrLk::WRITE_ENABLED);
});
self.scg0.rosccsr().modify(|w| {
w.set_rosccm(true);
});
while self.scg0.rosccsr().read().roscvld() != Roscvld::ENABLED_AND_VALID {}
}
Osc32KMode::LowPower {
coarse_amp_gain,

2
examples/mcxa5xx/Cargo.toml
View File

@@ -36,8 +36,6 @@ default-executor = [
custom-executor = [
"embassy-mcxa/custom-executor"
]
mcxa5xx = []
unstable-pac = []
[profile.release]
lto = true # better optimizations

39
examples/mcxa5xx/src/bin/clkout.rs
View File

@@ -4,7 +4,7 @@
use embassy_executor::Spawner;
use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4};
use embassy_mcxa::clocks::PoweredClock;
use embassy_mcxa::clocks::config::{Div8, Osc32KCapSel, Osc32KCoarseGain, Osc32KConfig, Osc32KMode, SoscConfig, SoscMode, SpllConfig, SpllMode, SpllSource};
use embassy_mcxa::clocks::config::{Div8, SoscConfig, SoscMode, SpllConfig, SpllMode, SpllSource};
use embassy_mcxa::gpio::{DriveStrength, Level, Output, SlewRate};
use embassy_time::Timer;
use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
@@ -32,21 +32,17 @@ async fn main(_spawner: Spawner) {
power: PoweredClock::NormalEnabledDeepSleepDisabled,
pll1_clk_div: Some(Div8::no_div()),
});
// TODO: These are wild guesses! They seem to work, I have no idea what these should be!
let mut osc = Osc32KConfig::default();
// TODO: Figure out OSC32K
// let mut osc = Osc32KConfig::default();
// osc.mode = Osc32KMode::HighPower {
// coarse_amp_gain: Osc32KCoarseGain::EsrRange0,
// xtal_cap_sel: Osc32KCapSel::Cap12PicoF,
// extal_cap_sel: Osc32KCapSel::Cap12PicoF,
// };
osc.mode = Osc32KMode::LowPower {
coarse_amp_gain: Osc32KCoarseGain::EsrRange0,
vbat_exceeds_3v0: true,
};
osc.vsys_domain_active = true;
osc.vdd_core_domain_active = true;
osc.vbat_domain_active = true;
cfg.clock_cfg.osc32k = Some(osc);
// osc.vsys_domain_active = true;
// osc.vdd_core_domain_active = true;
// osc.vbat_domain_active = true;
// cfg.clock_cfg.osc32k = Some(osc);
defmt::info!("init...");
let p = hal::init(cfg);
@@ -55,11 +51,11 @@ async fn main(_spawner: Spawner) {
let mut pin = p.P4_2;
let mut clkout = p.CLKOUT;
const K32_CONFIG: Config = Config {
sel: ClockOutSel::LpOsc,
div: Div4::no_div(),
level: PoweredClock::NormalEnabledDeepSleepDisabled,
};
// const K32_CONFIG: Config = Config {
// sel: ClockOutSel::LpOsc,
// div: Div4::no_div(),
// level: PoweredClock::NormalEnabledDeepSleepDisabled,
// };
const M4_CONFIG: Config = Config {
sel: ClockOutSel::Fro12M,
div: const { Div4::from_divisor(3).unwrap() },
@@ -78,12 +74,11 @@ async fn main(_spawner: Spawner) {
#[rustfmt::skip]
let configs = [
("32K -> /1 = 32K", K32_CONFIG), // no output
// this is "lp_osc", is that not clk_16k?
//
// ("12M -> /3 = 4M", M4_CONFIG), // good
// ("24M -> /12 = 2M", M2_CONFIG), // good
// ("12M-> /12 = 1M", M1_CONFIG), // good
// TODO: re-enable
// ("32K -> /1 = 32K", K32_CONFIG), // no output
("12M -> /3 = 4M", M4_CONFIG), // good
("24M -> /12 = 2M", M2_CONFIG), // good
("12M-> /12 = 1M", M1_CONFIG), // good
];
loop {