- Make DQSE / SIOO configurable
- Make write instruction configurable
- Fix bug where the address DTR was using the config for the instruction DTR instead of its own
- Configure DQS pin
Since the register structs are no-field structs with
`repr(transparent)`, we can use them in the LinearItem with `repr(C)`.
This allows the user to call the convenient named setter functions for
the registers instead of manually changing the bits of the u32.
- It is now possible to pass a linked-list table to the ring-buffer with
the `new_with_table()` function or use the `new()` function for a basic
ring-buffer setup.
- A `simple_ring_buffer_table()` function was added to the read and
write ring-buffers to generate the same table as the one created by
`new()` in case the user only wants to customize the default table
options.
- RegisterUpdaters have been removed as the user now has direct access
to the table and its items if needed.
See: https://github.com/elagil/embassy/pull/1#issuecomment-2891997294
See
https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2888810087
The default configuration of the channel which was done in `start()` is
now done in `new()` this allows overriding some settings through the new
`get_dma_channel` function. Only ringbuffers support this;
`LinkedListTransfer` and `Transfer` do not support that yet.
When a slave responds with a NACK in blocking I²C master mode, all subsequent transmissions send only the address followed immediately by a STOP.
This happens because the current implementation sets I2C_CR2.STOP = 1 whenever any error (including a NACK) occurs. As a result, the STOP bit is already set when the next transmission starts.
According to the reference manual: "If a NACK is received: […] a STOP condition is automatically sent […]"
This bug was not triggered until #4454 was merged.
Required on STM32WL with default HAL initialization.
The function is only available for adc_g0, but all
that have clock config should add implementations.
