Birk Tjelmeland
88c4274547
stm32/usart: fix blocking flush
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The PR in #2416 fixes buffered usart flushing,
but only for the async functions. This commit
introduces the same fixes to the blocking
functions.
2025-09-10 14:00:01 +02:00
Dario Nieuwenhuis
25e0ebf520
Merge pull request #4430 from fwolter/add-f1-remap
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Add STM32F1 AFIO remap
2025-09-05 22:45:57 +00:00
Dario Nieuwenhuis
23d5c7efd9
stm32/afio: fix accidentally always using AF number 0 on non-AFIO chips.
2025-09-06 00:39:18 +02:00
Dario Nieuwenhuis
a23c4b7bca
stm32/afio: make af_num() unavailable in afio chips.
2025-09-06 00:14:03 +02:00
Dario Nieuwenhuis
35f4ae378c
stm32/afio: make the A generic param only appear in chips with AFIO.
2025-09-05 23:44:25 +02:00
Dario Nieuwenhuis
7419b398bf
stm32/afio: use type inference for timer remaps as well.
2025-09-05 23:00:31 +02:00
Francisco José Gómez
59af53d53e
fix(embassy-stm32): Remove duplicate fn call, vestigial from earlier refcount implementation
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Refs: #4577
2025-09-05 15:31:12 -04:00
Fabian Wolter
a6562c4f03
Add STM32F1 AFIO remap
2025-09-05 21:15:46 +02:00
Dario Nieuwenhuis
6438068c16
Merge pull request #4368 from nikvoid/stm32-complementary-pwm-dma
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stm32: add `waveform_up` function for complementary PWM too
2025-09-05 16:56:18 +02:00
Dario Nieuwenhuis
4b27444e1c
Merge pull request #4359 from cbaechler/fix/stm32-l0-temperature-channel
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embassy-stm32: Fix temperature ADC channel for STM32L0 series
2025-09-05 16:56:07 +02:00
jake-taf
525c7fe1eb
OSPI RAM Support
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- Make DQSE / SIOO configurable
- Make write instruction configurable
- Fix bug where the address DTR was using the config for the instruction DTR instead of its own
- Configure DQS pin
2025-09-05 16:34:17 +02:00
Francisco José Gómez
46ce5ab697
chore(embassy-stm32): Update changelog
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Refs: #4577
2025-09-05 16:28:40 +02:00
Francisco José Gómez
d264c8ab31
fix(embassy-stm32): Prevent dropped DacChannel from disabling Dac peripheral if another DacChannel is still in scope
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Fix #4577 by counting references to DacChannel. Modeled after similar code in the `can` module.
2025-09-05 16:28:40 +02:00
Dario Nieuwenhuis
1c2fa92293
Merge pull request #4620 from embassy-rs/lolsai
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stm32: add i2s support for all versions, cleanup spi/i2s/sai versions.
2025-09-05 14:13:10 +00:00
Dario Nieuwenhuis
683ca6595f
stm32/spi: update for new version numbering, add i2s support for all versions.
2025-09-05 16:01:29 +02:00
Dario Nieuwenhuis
704c294162
Merge branch 'main' into adc_with_clock
2025-09-05 15:29:20 +02:00
Dario Nieuwenhuis
90d403fd0a
stm32: peri_v1_bar now enables cfgs peri_v1 and peri_v1_bar.
2025-09-05 15:19:22 +02:00
Dario Nieuwenhuis
60b640bd97
stm32/sai: update for new metapac, simplify cfgs.
2025-09-05 15:19:22 +02:00
Adrian Figueroa
2e2562d8dc
fix: ping-pong helper DMA direction
2025-09-05 14:43:43 +02:00
Adrian Figueroa
1e54841632
chore: add changelog entry
2025-09-05 14:43:43 +02:00
elagil
1e627cab29
refactor: make dma implementations match in interface
2025-09-05 14:43:29 +02:00
elagil
db7828538f
fix: consolidate naming
2025-09-05 14:43:29 +02:00
elagil
e9783ee28e
fix: build
2025-09-05 14:43:29 +02:00
etiennecollin
d3718c6d4e
fix: renamed simple table as per ST nomenclature
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Co-authored-by: elagil <elagil@takanome.de>
2025-09-05 14:43:29 +02:00
etiennecollin
51e7fafc3c
fix: removed unnecessary mut reference
2025-09-05 14:43:29 +02:00
etiennecollin
47bb14514f
feat: use register wrappers instead of u32 for LinearItem
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Since the register structs are no-field structs with
`repr(transparent)`, we can use them in the LinearItem with `repr(C)`.
This allows the user to call the convenient named setter functions for
the registers instead of manually changing the bits of the u32.
2025-09-05 14:43:29 +02:00
etiennecollin
50e2e2ec60
feat: add new_with_table() initializer for ring-buffers and removal of RegisterUpdaters
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- It is now possible to pass a linked-list table to the ring-buffer with
the `new_with_table()` function or use the `new()` function for a basic
ring-buffer setup.
- A `simple_ring_buffer_table()` function was added to the read and
write ring-buffers to generate the same table as the one created by
`new()` in case the user only wants to customize the default table
options.
- RegisterUpdaters have been removed as the user now has direct access
to the table and its items if needed.
See: https://github.com/elagil/embassy/pull/1#issuecomment-2891997294
2025-09-05 14:43:29 +02:00
etiennecollin
4291a092be
fix: moved channel configuration from new() to start()
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See this PR comment explaining why configuration in `new()` is a bad
idea:
https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889193736
2025-09-05 14:43:29 +02:00
etiennecollin
a2daa9739f
fix: removed functions exposing channel registers
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These functions could be used to cause UB.
2025-09-05 14:43:29 +02:00
etiennecollin
2f24568de0
feat: custom dma configuration using RegisterUpdaters struct
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See this PR comment:
https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889283939
2025-09-05 14:43:29 +02:00
etiennecollin
f67365a067
fix: suspend before reset
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This follows the procedure outlined in the STM32U5 reference manual at
page 696.
2025-09-05 14:43:29 +02:00
etiennecollin
4999069198
feat: use provided TransferOptions instead of defaults
2025-09-05 14:43:29 +02:00
etiennecollin
277c59857b
feat: custom DMA channel configuration
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See
https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2888810087
The default configuration of the channel which was done in `start()` is
now done in `new()` this allows overriding some settings through the new
`get_dma_channel` function. Only ringbuffers support this;
`LinkedListTransfer` and `Transfer` do not support that yet.
2025-09-05 14:43:29 +02:00
etiennecollin
c0b8e9c7e5
fix: writing reserved bits
2025-09-05 14:43:29 +02:00
etiennecollin
fec14213ea
fix: modified dma channel state management
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See
https://github.com/embassy-rs/embassy/pull/3923#discussion_r2094570176
2025-09-05 14:43:29 +02:00
elagil
7d224d94c4
fix: docstring
2025-09-05 14:43:29 +02:00
elagil
40a0d5d8f2
fix: build warnings
2025-09-05 14:43:29 +02:00
elagil
3d161e98a1
fix: simplify
2025-09-05 14:43:29 +02:00
elagil
7a62b8eee8
fix: build issues
2025-09-05 14:43:29 +02:00
elagil
a4d3b4b6ae
feat: wip, write buffer in halves
2025-09-05 14:43:29 +02:00
elagil
78364b966e
chore: change naming
2025-09-05 14:43:29 +02:00
elagil
2baa4399a7
fix: wip gpdma
2025-09-05 14:43:29 +02:00
elagil
50224583db
fix: load/store ordering
2025-09-05 14:43:29 +02:00
elagil
bfd82ff82c
fix: read transfer options
2025-09-05 14:43:29 +02:00
elagil
1541f1e0c2
chore: clean up transfer options
2025-09-05 14:43:29 +02:00
elagil
be88187591
fix: transfer options
2025-09-05 14:43:29 +02:00
elagil
f0fc1a15da
fix: disable half-complete interrupt
2025-09-05 14:43:29 +02:00
elagil
51b28aaa31
style: formatting
2025-09-05 14:43:29 +02:00
elagil
4155adbf8a
feat: ping-pong buffers
2025-09-05 14:43:29 +02:00
elagil
cf5b1ea9f5
feat: gpdma support (wip)
2025-09-05 14:43:29 +02:00
