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Simplify peripheral resets (#3720)

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* Update PAC to fix naming inconsistencies, simplify reset code

* Update PAC and simplify

* Remove mcpwm1 reset

* Fix gen register name

* Fixup

* Finalize PAC rev
This commit is contained in:
Dániel Buga 2025-06-30 17:09:21 +02:00 committed by GitHub
parent 541240b460
commit 03a3b6f5d6
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GPG Key ID: B5690EEEBB952194
5 changed files with 319 additions and 451 deletions
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14
esp-hal/Cargo.toml
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@ -70,13 +70,13 @@ ufmt-write = { version = "0.1.0", optional = true }
# IMPORTANT: # IMPORTANT:
# Each supported device MUST have its PAC included below along with a # Each supported device MUST have its PAC included below along with a
# corresponding feature. # corresponding feature.
esp32 = { version = "0.37.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32 = { version = "0.37.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
esp32c2 = { version = "0.26.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32c2 = { version = "0.26.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
esp32c3 = { version = "0.29.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32c3 = { version = "0.29.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
esp32c6 = { version = "0.20.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32c6 = { version = "0.20.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
esp32h2 = { version = "0.16.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32h2 = { version = "0.16.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
esp32s2 = { version = "0.28.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32s2 = { version = "0.28.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
esp32s3 = { version = "0.32.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "7707ae7", optional = true } esp32s3 = { version = "0.32.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "782de0b", optional = true }
[target.'cfg(target_arch = "riscv32")'.dependencies] [target.'cfg(target_arch = "riscv32")'.dependencies]
riscv = { version = "0.12.1" } riscv = { version = "0.12.1" }

4
esp-hal/src/i2c/master/mod.rs
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@ -2379,7 +2379,7 @@ impl Driver<'_> {
self.reset_before_transmission(); self.reset_before_transmission();
// Short circuit for zero length writes without start or end as that would be an // Short circuit for zero length writes without start or end as that would be an
// invalid operation write lengths in the TRM (at least for ESP32-S3) are 1-255 // invalid operation write lengths in the TRM (at least for ESP32-S3) are 1-255
if bytes.is_empty() && !start && !stop { if bytes.is_empty() && !start && !stop {
return Ok(()); return Ok(());
} }
@ -2446,7 +2446,7 @@ impl Driver<'_> {
self.reset_before_transmission(); self.reset_before_transmission();
// Short circuit for zero length writes without start or end as that would be an // Short circuit for zero length writes without start or end as that would be an
// invalid operation write lengths in the TRM (at least for ESP32-S3) are 1-255 // invalid operation write lengths in the TRM (at least for ESP32-S3) are 1-255
if bytes.is_empty() && !start && !stop { if bytes.is_empty() && !start && !stop {
return Ok(()); return Ok(());
} }

3
esp-hal/src/mcpwm/operator.rs
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@ -320,8 +320,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,
// SAFETY: // SAFETY:
// `bits` is a valid bit pattern // `bits` is a valid bit pattern
ch.r#gen((!IS_A) as usize) ch.gen_((!IS_A) as usize).write(|w| unsafe { w.bits(bits) });
.write(|w| unsafe { w.bits(bits) });
} }
/// Set how a new timestamp syncs with the timer /// Set how a new timestamp syncs with the timer

4
esp-hal/src/soc/esp32/trng.rs
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@ -20,11 +20,11 @@ pub(crate) fn ensure_randomness() {
// periph_module_enable(PERIPH_I2S0_MODULE); // periph_module_enable(PERIPH_I2S0_MODULE);
dport dport
.perip_clk_en() .perip_clk_en()
.modify(|_, w| w.i2c0_ext0_clk_en().set_bit()); .modify(|_, w| w.i2c_ext0_clk_en().set_bit());
dport dport
.perip_rst_en() .perip_rst_en()
.modify(|_, w| w.i2c0_ext0_rst().clear_bit()); .modify(|_, w| w.i2c_ext0_rst().clear_bit());
sens.sar_start_force() sens.sar_start_force()
.modify(|_, w| w.ulp_cp_force_start_top().clear_bit()); .modify(|_, w| w.ulp_cp_force_start_top().clear_bit());

745
esp-hal/src/system.rs
View File

@ -321,7 +321,7 @@ impl PeripheralClockControl {
let system = SYSTEM::regs(); let system = SYSTEM::regs();
#[cfg(esp32)] #[cfg(esp32)]
let (perip_clk_en0, peri_clk_en) = { (&system.perip_clk_en(), &system.peri_clk_en()) }; let (perip_clk_en0, perip_clk_en1) = { (&system.perip_clk_en(), &system.peri_clk_en()) };
#[cfg(not(esp32))] #[cfg(not(esp32))]
let perip_clk_en0 = &system.perip_clk_en0(); let perip_clk_en0 = &system.perip_clk_en0();
@ -337,11 +337,7 @@ impl PeripheralClockControl {
Peripheral::Spi3 => { Peripheral::Spi3 => {
perip_clk_en0.modify(|_, w| w.spi3_clk_en().bit(enable)); perip_clk_en0.modify(|_, w| w.spi3_clk_en().bit(enable));
} }
#[cfg(all(soc_has_i2c0, esp32))] #[cfg(soc_has_i2c0)]
Peripheral::I2cExt0 => {
perip_clk_en0.modify(|_, w| w.i2c0_ext0_clk_en().bit(enable));
}
#[cfg(all(soc_has_i2c0, not(esp32)))]
Peripheral::I2cExt0 => { Peripheral::I2cExt0 => {
perip_clk_en0.modify(|_, w| w.i2c_ext0_clk_en().bit(enable)); perip_clk_en0.modify(|_, w| w.i2c_ext0_clk_en().bit(enable));
} }
@ -387,16 +383,11 @@ impl PeripheralClockControl {
perip_clk_en0.modify(|_, w| w.spi3_dma_clk_en().bit(enable)); perip_clk_en0.modify(|_, w| w.spi3_dma_clk_en().bit(enable));
perip_clk_en1.modify(|_, w| w.crypto_dma_clk_en().bit(enable)); perip_clk_en1.modify(|_, w| w.crypto_dma_clk_en().bit(enable));
} }
#[cfg(esp32c3)] #[cfg(soc_has_i2s0)]
Peripheral::I2s0 => {
// on ESP32-C3 note that i2s1_clk_en / rst is really I2s0
perip_clk_en0.modify(|_, w| w.i2s1_clk_en().bit(enable));
}
#[cfg(any(esp32s3, esp32, esp32s2))]
Peripheral::I2s0 => { Peripheral::I2s0 => {
perip_clk_en0.modify(|_, w| w.i2s0_clk_en().bit(enable)); perip_clk_en0.modify(|_, w| w.i2s0_clk_en().bit(enable));
} }
#[cfg(any(esp32s3, esp32))] #[cfg(soc_has_i2s1)]
Peripheral::I2s1 => { Peripheral::I2s1 => {
perip_clk_en0.modify(|_, w| w.i2s1_clk_en().bit(enable)); perip_clk_en0.modify(|_, w| w.i2s1_clk_en().bit(enable));
} }
@ -408,11 +399,7 @@ impl PeripheralClockControl {
Peripheral::Twai0 => { Peripheral::Twai0 => {
perip_clk_en0.modify(|_, w| w.twai_clk_en().bit(enable)); perip_clk_en0.modify(|_, w| w.twai_clk_en().bit(enable));
} }
#[cfg(esp32)] #[cfg(soc_has_aes)]
Peripheral::Aes => {
peri_clk_en.modify(|r, w| unsafe { w.bits(r.bits() | enable as u32) });
}
#[cfg(any(esp32c3, esp32s2, esp32s3))]
Peripheral::Aes => { Peripheral::Aes => {
perip_clk_en1.modify(|_, w| w.crypto_aes_clk_en().bit(enable)); perip_clk_en1.modify(|_, w| w.crypto_aes_clk_en().bit(enable));
} }
@ -430,7 +417,6 @@ impl PeripheralClockControl {
} }
#[cfg(soc_has_sha)] #[cfg(soc_has_sha)]
Peripheral::Sha => { Peripheral::Sha => {
#[cfg(not(esp32))]
perip_clk_en1.modify(|_, w| w.crypto_sha_clk_en().bit(enable)); perip_clk_en1.modify(|_, w| w.crypto_sha_clk_en().bit(enable));
} }
#[cfg(esp32c3)] #[cfg(esp32c3)]
@ -459,7 +445,7 @@ impl PeripheralClockControl {
} }
#[cfg(all(rsa, esp32))] #[cfg(all(rsa, esp32))]
Peripheral::Rsa => { Peripheral::Rsa => {
peri_clk_en.modify(|r, w| unsafe { w.bits(r.bits() | ((enable as u32) << 2)) }); perip_clk_en1.modify(|_, w| w.crypto_rsa_clk_en().bit(enable));
} }
#[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))] #[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))]
Peripheral::Rsa => { Peripheral::Rsa => {
@ -494,223 +480,9 @@ impl PeripheralClockControl {
/// Resets the given peripheral /// Resets the given peripheral
pub(crate) fn reset(peripheral: Peripheral) { pub(crate) fn reset(peripheral: Peripheral) {
debug!("Reset {:?}", peripheral); debug!("Reset {:?}", peripheral);
let system = SYSTEM::regs();
#[cfg(esp32)] assert_peri_reset(peripheral, true);
let (perip_rst_en0, peri_rst_en) = (system.perip_rst_en(), system.peri_rst_en()); assert_peri_reset(peripheral, false);
#[cfg(not(esp32))]
let perip_rst_en0 = system.perip_rst_en0();
#[cfg(any(esp32c2, esp32c3, esp32s2, esp32s3))]
let perip_rst_en1 = system.perip_rst_en1();
critical_section::with(|_cs| match peripheral {
#[cfg(soc_has_spi2)]
Peripheral::Spi2 => {
perip_rst_en0.modify(|_, w| w.spi2_rst().set_bit());
perip_rst_en0.modify(|_, w| w.spi2_rst().clear_bit());
}
#[cfg(soc_has_spi3)]
Peripheral::Spi3 => {
perip_rst_en0.modify(|_, w| w.spi3_rst().set_bit());
perip_rst_en0.modify(|_, w| w.spi3_rst().clear_bit());
}
#[cfg(all(soc_has_i2c0, esp32))]
Peripheral::I2cExt0 => {
perip_rst_en0.modify(|_, w| w.i2c0_ext0_rst().set_bit());
perip_rst_en0.modify(|_, w| w.i2c0_ext0_rst().clear_bit());
}
#[cfg(all(soc_has_i2c0, not(esp32)))]
Peripheral::I2cExt0 => {
perip_rst_en0.modify(|_, w| w.i2c_ext0_rst().set_bit());
perip_rst_en0.modify(|_, w| w.i2c_ext0_rst().clear_bit());
}
#[cfg(soc_has_i2c1)]
Peripheral::I2cExt1 => {
perip_rst_en0.modify(|_, w| w.i2c_ext1_rst().set_bit());
perip_rst_en0.modify(|_, w| w.i2c_ext1_rst().clear_bit());
}
#[cfg(soc_has_rmt)]
Peripheral::Rmt => {
perip_rst_en0.modify(|_, w| w.rmt_rst().set_bit());
perip_rst_en0.modify(|_, w| w.rmt_rst().clear_bit());
}
#[cfg(soc_has_ledc)]
Peripheral::Ledc => {
perip_rst_en0.modify(|_, w| w.ledc_rst().set_bit());
perip_rst_en0.modify(|_, w| w.ledc_rst().clear_bit());
}
#[cfg(soc_has_mcpwm0)]
Peripheral::Mcpwm0 => {
perip_rst_en0.modify(|_, w| w.pwm0_rst().set_bit());
perip_rst_en0.modify(|_, w| w.pwm0_rst().clear_bit());
}
#[cfg(soc_has_mcpwm1)]
Peripheral::Mcpwm1 => {
perip_rst_en0.modify(|_, w| w.pwm1_rst().set_bit());
perip_rst_en0.modify(|_, w| w.pwm1_rst().clear_bit());
}
#[cfg(soc_has_pcnt)]
Peripheral::Pcnt => {
perip_rst_en0.modify(|_, w| w.pcnt_rst().set_bit());
perip_rst_en0.modify(|_, w| w.pcnt_rst().clear_bit());
}
#[cfg(soc_has_apb_saradc)]
Peripheral::ApbSarAdc => {
perip_rst_en0.modify(|_, w| w.apb_saradc_rst().set_bit());
perip_rst_en0.modify(|_, w| w.apb_saradc_rst().clear_bit());
}
#[cfg(gdma)]
Peripheral::Gdma => {
perip_rst_en1.modify(|_, w| w.dma_rst().set_bit());
perip_rst_en1.modify(|_, w| w.dma_rst().clear_bit());
}
#[cfg(esp32)]
Peripheral::Dma => {
perip_rst_en0.modify(|_, w| w.spi_dma_rst().set_bit());
perip_rst_en0.modify(|_, w| w.spi_dma_rst().clear_bit());
}
#[cfg(esp32s2)]
Peripheral::Dma => {
perip_rst_en0.modify(|_, w| w.spi2_dma_rst().set_bit());
perip_rst_en0.modify(|_, w| w.spi2_dma_rst().clear_bit());
perip_rst_en0.modify(|_, w| w.spi3_dma_rst().set_bit());
perip_rst_en0.modify(|_, w| w.spi3_dma_rst().clear_bit());
perip_rst_en1.modify(|_, w| w.crypto_dma_rst().set_bit());
perip_rst_en1.modify(|_, w| w.crypto_dma_rst().clear_bit());
}
#[cfg(esp32c3)]
Peripheral::I2s0 => {
// on ESP32-C3 note that i2s1_clk_en / rst is really I2s0
perip_rst_en0.modify(|_, w| w.i2s1_rst().set_bit());
perip_rst_en0.modify(|_, w| w.i2s1_rst().clear_bit());
}
#[cfg(any(esp32s3, esp32, esp32s2))]
Peripheral::I2s0 => {
perip_rst_en0.modify(|_, w| w.i2s0_rst().set_bit());
perip_rst_en0.modify(|_, w| w.i2s0_rst().clear_bit());
}
#[cfg(any(esp32s3, esp32))]
Peripheral::I2s1 => {
perip_rst_en0.modify(|_, w| w.i2s1_rst().set_bit());
perip_rst_en0.modify(|_, w| w.i2s1_rst().clear_bit());
}
#[cfg(soc_has_usb0)]
Peripheral::Usb => {
perip_rst_en0.modify(|_, w| w.usb_rst().set_bit());
perip_rst_en0.modify(|_, w| w.usb_rst().clear_bit());
}
#[cfg(soc_has_twai0)]
Peripheral::Twai0 => {
perip_rst_en0.modify(|_, w| w.twai_rst().set_bit());
perip_rst_en0.modify(|_, w| w.twai_rst().clear_bit());
}
#[cfg(esp32)]
Peripheral::Aes => {
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() | 1) });
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() & (!1)) });
}
#[cfg(any(esp32c3, esp32s2, esp32s3))]
Peripheral::Aes => {
perip_rst_en1.modify(|_, w| w.crypto_aes_rst().set_bit());
perip_rst_en1.modify(|_, w| w.crypto_aes_rst().clear_bit());
}
#[cfg(soc_has_timg0)]
Peripheral::Timg0 => {
#[cfg(any(esp32c3, esp32s2, esp32s3))]
perip_rst_en0.modify(|_, w| w.timers_rst().set_bit());
perip_rst_en0.modify(|_, w| w.timergroup_rst().set_bit());
#[cfg(any(esp32c3, esp32s2, esp32s3))]
perip_rst_en0.modify(|_, w| w.timers_rst().clear_bit());
perip_rst_en0.modify(|_, w| w.timergroup_rst().clear_bit());
}
#[cfg(soc_has_timg1)]
Peripheral::Timg1 => {
#[cfg(any(esp32c3, esp32s2, esp32s3))]
perip_rst_en0.modify(|_, w| w.timers_rst().set_bit());
perip_rst_en0.modify(|_, w| w.timergroup1_rst().set_bit());
#[cfg(any(esp32c3, esp32s2, esp32s3))]
perip_rst_en0.modify(|_, w| w.timers_rst().clear_bit());
perip_rst_en0.modify(|_, w| w.timergroup1_rst().clear_bit());
}
#[cfg(soc_has_sha)]
Peripheral::Sha => {
#[cfg(not(esp32))]
perip_rst_en1.modify(|_, w| w.crypto_sha_rst().set_bit());
#[cfg(not(esp32))]
perip_rst_en1.modify(|_, w| w.crypto_sha_rst().clear_bit());
}
#[cfg(esp32c3)]
Peripheral::UsbDevice => {
perip_rst_en0.modify(|_, w| w.usb_device_rst().set_bit());
perip_rst_en0.modify(|_, w| w.usb_device_rst().clear_bit());
}
#[cfg(esp32s3)]
Peripheral::UsbDevice => {
perip_rst_en1.modify(|_, w| w.usb_device_rst().set_bit());
perip_rst_en1.modify(|_, w| w.usb_device_rst().clear_bit());
}
#[cfg(soc_has_uart0)]
Peripheral::Uart0 => {
perip_rst_en0.modify(|_, w| w.uart_rst().set_bit());
perip_rst_en0.modify(|_, w| w.uart_rst().clear_bit());
}
#[cfg(soc_has_uart1)]
Peripheral::Uart1 => {
perip_rst_en0.modify(|_, w| w.uart1_rst().set_bit());
perip_rst_en0.modify(|_, w| w.uart1_rst().clear_bit());
}
#[cfg(all(soc_has_uart2, esp32s3))]
Peripheral::Uart2 => {
perip_rst_en1.modify(|_, w| w.uart2_rst().set_bit());
perip_rst_en1.modify(|_, w| w.uart2_rst().clear_bit());
}
#[cfg(all(soc_has_uart2, esp32))]
Peripheral::Uart2 => {
perip_rst_en0.modify(|_, w| w.uart2_rst().set_bit());
perip_rst_en0.modify(|_, w| w.uart2_rst().clear_bit());
}
#[cfg(all(rsa, esp32))]
Peripheral::Rsa => {
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 2)) });
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << 2)) });
}
#[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))]
Peripheral::Rsa => {
perip_rst_en1.modify(|_, w| w.crypto_rsa_rst().set_bit());
perip_rst_en1.modify(|_, w| w.crypto_rsa_rst().clear_bit());
}
#[cfg(soc_has_hmac)]
Peripheral::Hmac => {
perip_rst_en1.modify(|_, w| w.crypto_hmac_rst().set_bit());
perip_rst_en1.modify(|_, w| w.crypto_hmac_rst().clear_bit());
}
#[cfg(soc_has_ecc)]
Peripheral::Ecc => {
perip_rst_en1.modify(|_, w| w.crypto_ecc_rst().set_bit());
perip_rst_en1.modify(|_, w| w.crypto_ecc_rst().clear_bit());
}
#[cfg(soc_has_lcd_cam)]
Peripheral::LcdCam => {
perip_rst_en1.modify(|_, w| w.lcd_cam_rst().set_bit());
perip_rst_en1.modify(|_, w| w.lcd_cam_rst().clear_bit());
}
#[cfg(soc_has_systimer)]
Peripheral::Systimer => {
perip_rst_en0.modify(|_, w| w.systimer_rst().set_bit());
perip_rst_en0.modify(|_, w| w.systimer_rst().clear_bit());
}
#[cfg(all(tsens, esp32c6))]
Peripheral::Tsens => {
perip_rst_en0.modify(|_, w| w.tsens_rst().set_bit());
perip_rst_en0.modify(|_, w| w.tsens_rst().clear_bit());
}
#[cfg(all(tsens, esp32c3))]
Peripheral::Tsens => {
perip_rst_en1.modify(|_, w| w.tsens_rst().set_bit());
perip_rst_en1.modify(|_, w| w.tsens_rst().clear_bit());
}
});
} }
} }
@ -782,10 +554,8 @@ impl PeripheralClockControl {
if enable { if enable {
// use Xtal clk-src // use Xtal clk-src
system.twai0_func_clk_conf().modify(|_, w| { system.twai0_func_clk_conf().modify(|_, w| {
w.twai0_func_clk_en() w.twai0_func_clk_en().set_bit();
.set_bit() w.twai0_func_clk_sel().variant(false)
.twai0_func_clk_sel()
.variant(false)
}); });
} }
} }
@ -876,13 +646,10 @@ impl PeripheralClockControl {
} }
#[cfg(tsens)] #[cfg(tsens)]
Peripheral::Tsens => { Peripheral::Tsens => {
system system.tsens_clk_conf().modify(|_, w| {
.tsens_clk_conf() w.tsens_clk_en().bit(enable);
.modify(|_, w| w.tsens_clk_en().bit(enable)); w.tsens_clk_sel().bit(enable)
});
system
.tsens_clk_conf()
.modify(|_, w| w.tsens_clk_sel().bit(enable));
} }
} }
} }
@ -891,199 +658,302 @@ impl PeripheralClockControl {
pub(crate) fn reset(peripheral: Peripheral) { pub(crate) fn reset(peripheral: Peripheral) {
debug!("Reset {:?}", peripheral); debug!("Reset {:?}", peripheral);
let system = SYSTEM::regs(); assert_peri_reset(peripheral, true);
assert_peri_reset(peripheral, false);
}
}
match peripheral { #[cfg(not(any(esp32c6, esp32h2)))]
#[cfg(soc_has_spi2)] /// Resets the given peripheral
Peripheral::Spi2 => { pub(crate) fn assert_peri_reset(peripheral: Peripheral, reset: bool) {
system.spi2_conf().modify(|_, w| w.spi2_rst_en().set_bit()); let system = SYSTEM::regs();
system
.spi2_conf() #[cfg(esp32)]
.modify(|_, w| w.spi2_rst_en().clear_bit()); let (perip_rst_en0, perip_rst_en1) = (system.perip_rst_en(), system.peri_rst_en());
} #[cfg(not(esp32))]
#[cfg(soc_has_i2c0)] let perip_rst_en0 = system.perip_rst_en0();
Peripheral::I2cExt0 => {
#[cfg(any(esp32c6, esp32h2))] #[cfg(any(esp32c2, esp32c3, esp32s2, esp32s3))]
{ let perip_rst_en1 = system.perip_rst_en1();
system.i2c0_conf().modify(|_, w| w.i2c0_rst_en().set_bit());
system critical_section::with(|_cs| match peripheral {
.i2c0_conf() #[cfg(soc_has_spi2)]
.modify(|_, w| w.i2c0_rst_en().clear_bit()); Peripheral::Spi2 => {
perip_rst_en0.modify(|_, w| w.spi2_rst().bit(reset));
}
#[cfg(soc_has_spi3)]
Peripheral::Spi3 => {
perip_rst_en0.modify(|_, w| w.spi3_rst().bit(reset));
}
#[cfg(soc_has_i2c0)]
Peripheral::I2cExt0 => {
perip_rst_en0.modify(|_, w| w.i2c_ext0_rst().bit(reset));
}
#[cfg(soc_has_i2c1)]
Peripheral::I2cExt1 => {
perip_rst_en0.modify(|_, w| w.i2c_ext1_rst().bit(reset));
}
#[cfg(soc_has_rmt)]
Peripheral::Rmt => {
perip_rst_en0.modify(|_, w| w.rmt_rst().bit(reset));
}
#[cfg(soc_has_ledc)]
Peripheral::Ledc => {
perip_rst_en0.modify(|_, w| w.ledc_rst().bit(reset));
}
#[cfg(soc_has_mcpwm0)]
Peripheral::Mcpwm0 => {
perip_rst_en0.modify(|_, w| w.pwm0_rst().bit(reset));
}
#[cfg(soc_has_mcpwm1)]
Peripheral::Mcpwm1 => {
perip_rst_en0.modify(|_, w| w.pwm1_rst().bit(reset));
}
#[cfg(soc_has_pcnt)]
Peripheral::Pcnt => {
perip_rst_en0.modify(|_, w| w.pcnt_rst().bit(reset));
}
#[cfg(soc_has_apb_saradc)]
Peripheral::ApbSarAdc => {
perip_rst_en0.modify(|_, w| w.apb_saradc_rst().bit(reset));
}
#[cfg(gdma)]
Peripheral::Gdma => {
perip_rst_en1.modify(|_, w| w.dma_rst().bit(reset));
}
#[cfg(esp32)]
Peripheral::Dma => {
perip_rst_en0.modify(|_, w| w.spi_dma_rst().bit(reset));
}
#[cfg(esp32s2)]
Peripheral::Dma => {
perip_rst_en0.modify(|_, w| w.spi2_dma_rst().bit(reset));
perip_rst_en0.modify(|_, w| w.spi3_dma_rst().bit(reset));
perip_rst_en1.modify(|_, w| w.crypto_dma_rst().bit(reset));
}
#[cfg(soc_has_i2s0)]
Peripheral::I2s0 => {
perip_rst_en0.modify(|_, w| w.i2s0_rst().bit(reset));
}
#[cfg(soc_has_i2s1)]
Peripheral::I2s1 => {
perip_rst_en0.modify(|_, w| w.i2s1_rst().bit(reset));
}
#[cfg(soc_has_usb0)]
Peripheral::Usb => {
perip_rst_en0.modify(|_, w| w.usb_rst().bit(reset));
}
#[cfg(soc_has_twai0)]
Peripheral::Twai0 => {
perip_rst_en0.modify(|_, w| w.twai_rst().bit(reset));
}
#[cfg(soc_has_aes)]
Peripheral::Aes => {
perip_rst_en1.modify(|_, w| w.crypto_aes_rst().bit(reset));
}
#[cfg(soc_has_timg0)]
Peripheral::Timg0 => {
#[cfg(any(esp32c3, esp32s2, esp32s3))]
perip_rst_en0.modify(|_, w| w.timers_rst().bit(reset));
perip_rst_en0.modify(|_, w| w.timergroup_rst().bit(reset));
}
#[cfg(soc_has_timg1)]
Peripheral::Timg1 => {
#[cfg(any(esp32c3, esp32s2, esp32s3))]
perip_rst_en0.modify(|_, w| w.timers_rst().bit(reset));
perip_rst_en0.modify(|_, w| w.timergroup1_rst().bit(reset));
}
#[cfg(soc_has_sha)]
Peripheral::Sha => {
perip_rst_en1.modify(|_, w| w.crypto_sha_rst().bit(reset));
}
#[cfg(soc_has_usb_device)]
Peripheral::UsbDevice => {
cfg_if::cfg_if! {
if #[cfg(esp32c3)] {
perip_rst_en0.modify(|_, w| w.usb_device_rst().bit(reset));
} else {
perip_rst_en1.modify(|_, w| w.usb_device_rst().bit(reset));
} }
} }
#[cfg(soc_has_i2c1)] }
Peripheral::I2cExt1 => { #[cfg(soc_has_uart0)]
#[cfg(esp32h2)] Peripheral::Uart0 => {
{ perip_rst_en0.modify(|_, w| w.uart_rst().bit(reset));
system.i2c1_conf().modify(|_, w| w.i2c1_rst_en().set_bit()); }
system #[cfg(soc_has_uart1)]
.i2c1_conf() Peripheral::Uart1 => {
.modify(|_, w| w.i2c1_rst_en().clear_bit()); perip_rst_en0.modify(|_, w| w.uart1_rst().bit(reset));
}
#[cfg(soc_has_uart2)]
Peripheral::Uart2 => {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
perip_rst_en0.modify(|_, w| w.uart2_rst().bit(reset));
} else {
perip_rst_en1.modify(|_, w| w.uart2_rst().bit(reset));
} }
} }
#[cfg(soc_has_rmt)] }
Peripheral::Rmt => { #[cfg(soc_has_rsa)]
system.rmt_conf().modify(|_, w| w.rmt_rst_en().set_bit()); Peripheral::Rsa => {
system.rmt_conf().modify(|_, w| w.rmt_rst_en().clear_bit()); perip_rst_en1.modify(|_, w| w.crypto_rsa_rst().bit(reset));
} }
#[cfg(soc_has_ledc)] #[cfg(soc_has_hmac)]
Peripheral::Ledc => { Peripheral::Hmac => {
system.ledc_conf().modify(|_, w| w.ledc_rst_en().set_bit()); perip_rst_en1.modify(|_, w| w.crypto_hmac_rst().bit(reset));
system }
.ledc_conf() #[cfg(soc_has_ecc)]
.modify(|_, w| w.ledc_rst_en().clear_bit()); Peripheral::Ecc => {
} perip_rst_en1.modify(|_, w| w.crypto_ecc_rst().bit(reset));
#[cfg(soc_has_mcpwm0)] }
Peripheral::Mcpwm0 => { #[cfg(soc_has_lcd_cam)]
system.pwm_conf().modify(|_, w| w.pwm_rst_en().set_bit()); Peripheral::LcdCam => {
system.pwm_conf().modify(|_, w| w.pwm_rst_en().clear_bit()); perip_rst_en1.modify(|_, w| w.lcd_cam_rst().bit(reset));
} }
#[cfg(soc_has_mcpwm1)] #[cfg(soc_has_systimer)]
Peripheral::Mcpwm1 => { Peripheral::Systimer => {
system.pwm_conf.modify(|_, w| w.pwm_rst_en().set_bit()); perip_rst_en0.modify(|_, w| w.systimer_rst().bit(reset));
system.pwm_conf.modify(|_, w| w.pwm_rst_en().clear_bit()); }
} #[cfg(all(tsens, esp32c6))]
#[cfg(soc_has_apb_saradc)] Peripheral::Tsens => {
Peripheral::ApbSarAdc => { perip_rst_en0.modify(|_, w| w.tsens_rst().bit(reset));
system }
.saradc_conf() #[cfg(all(tsens, esp32c3))]
.modify(|_, w| w.saradc_reg_rst_en().set_bit()); Peripheral::Tsens => {
system perip_rst_en1.modify(|_, w| w.tsens_rst().bit(reset));
.saradc_conf() }
.modify(|_, w| w.saradc_reg_rst_en().clear_bit()); });
} }
#[cfg(gdma)]
Peripheral::Gdma => { #[cfg(any(esp32c6, esp32h2))]
system.gdma_conf().modify(|_, w| w.gdma_rst_en().set_bit()); fn assert_peri_reset(peripheral: Peripheral, reset: bool) {
system let system = SYSTEM::regs();
.gdma_conf()
.modify(|_, w| w.gdma_rst_en().clear_bit()); match peripheral {
} #[cfg(soc_has_spi2)]
#[cfg(soc_has_i2s0)] Peripheral::Spi2 => {
Peripheral::I2s0 => { system.spi2_conf().modify(|_, w| w.spi2_rst_en().bit(reset));
system.i2s_conf().modify(|_, w| w.i2s_rst_en().set_bit()); }
system.i2s_conf().modify(|_, w| w.i2s_rst_en().clear_bit()); #[cfg(soc_has_i2c0)]
} Peripheral::I2cExt0 => {
#[cfg(soc_has_twai0)] system.i2c0_conf().modify(|_, w| w.i2c0_rst_en().bit(reset));
Peripheral::Twai0 => { }
system #[cfg(soc_has_i2c1)]
.twai0_conf() Peripheral::I2cExt1 => {
.modify(|_, w| w.twai0_rst_en().set_bit()); system.i2c1_conf().modify(|_, w| w.i2c1_rst_en().bit(reset));
system }
.twai0_conf() #[cfg(soc_has_rmt)]
.modify(|_, w| w.twai0_rst_en().clear_bit()); Peripheral::Rmt => {
} system.rmt_conf().modify(|_, w| w.rmt_rst_en().bit(reset));
#[cfg(soc_has_twai1)] }
Peripheral::Twai1 => { #[cfg(soc_has_ledc)]
system Peripheral::Ledc => {
.twai1_conf() system.ledc_conf().modify(|_, w| w.ledc_rst_en().bit(reset));
.modify(|_, w| w.twai1_rst_en().set_bit()); }
system #[cfg(soc_has_mcpwm0)]
.twai1_conf() Peripheral::Mcpwm0 => {
.modify(|_, w| w.twai1_rst_en().clear_bit()); system.pwm_conf().modify(|_, w| w.pwm_rst_en().bit(reset));
} }
#[cfg(soc_has_aes)] #[cfg(soc_has_apb_saradc)]
Peripheral::Aes => { Peripheral::ApbSarAdc => {
system.aes_conf().modify(|_, w| w.aes_rst_en().set_bit()); system
system.aes_conf().modify(|_, w| w.aes_rst_en().clear_bit()); .saradc_conf()
} .modify(|_, w| w.saradc_reg_rst_en().bit(reset));
#[cfg(soc_has_pcnt)] }
Peripheral::Pcnt => { #[cfg(gdma)]
system.pcnt_conf().modify(|_, w| w.pcnt_rst_en().set_bit()); Peripheral::Gdma => {
system system.gdma_conf().modify(|_, w| w.gdma_rst_en().bit(reset));
.pcnt_conf() }
.modify(|_, w| w.pcnt_rst_en().clear_bit()); #[cfg(soc_has_i2s0)]
} Peripheral::I2s0 => {
#[cfg(soc_has_timg0)] system.i2s_conf().modify(|_, w| w.i2s_rst_en().bit(reset));
Peripheral::Timg0 => { }
// no reset? #[cfg(soc_has_twai0)]
} Peripheral::Twai0 => {
#[cfg(soc_has_timg1)] system
Peripheral::Timg1 => { .twai0_conf()
// no reset? .modify(|_, w| w.twai0_rst_en().bit(reset));
} }
#[cfg(soc_has_sha)] #[cfg(soc_has_twai1)]
Peripheral::Sha => { Peripheral::Twai1 => {
system.sha_conf().modify(|_, w| w.sha_rst_en().set_bit()); system
system.sha_conf().modify(|_, w| w.sha_rst_en().clear_bit()); .twai1_conf()
} .modify(|_, w| w.twai1_rst_en().bit(reset));
#[cfg(soc_has_usb_device)] }
Peripheral::UsbDevice => { #[cfg(soc_has_aes)]
system Peripheral::Aes => {
.usb_device_conf() system.aes_conf().modify(|_, w| w.aes_rst_en().bit(reset));
.modify(|_, w| w.usb_device_rst_en().set_bit()); }
system #[cfg(soc_has_pcnt)]
.usb_device_conf() Peripheral::Pcnt => {
.modify(|_, w| w.usb_device_rst_en().clear_bit()); system.pcnt_conf().modify(|_, w| w.pcnt_rst_en().bit(reset));
} }
#[cfg(soc_has_uart0)] #[cfg(soc_has_timg0)]
Peripheral::Uart0 => { Peripheral::Timg0 => {
system.uart(0).conf().modify(|_, w| w.rst_en().set_bit()); // no reset?
system.uart(0).conf().modify(|_, w| w.rst_en().clear_bit()); }
} #[cfg(soc_has_timg1)]
#[cfg(soc_has_uart1)] Peripheral::Timg1 => {
Peripheral::Uart1 => { // no reset?
system.uart(1).conf().modify(|_, w| w.rst_en().set_bit()); }
system.uart(1).conf().modify(|_, w| w.rst_en().clear_bit()); #[cfg(soc_has_sha)]
} Peripheral::Sha => {
#[cfg(soc_has_rsa)] system.sha_conf().modify(|_, w| w.sha_rst_en().bit(reset));
Peripheral::Rsa => { }
system.rsa_conf().modify(|_, w| w.rsa_rst_en().set_bit()); #[cfg(soc_has_usb_device)]
system.rsa_conf().modify(|_, w| w.rsa_rst_en().clear_bit()); Peripheral::UsbDevice => {
} system
#[cfg(soc_has_parl_io)] .usb_device_conf()
Peripheral::ParlIo => { .modify(|_, w| w.usb_device_rst_en().bit(reset));
system }
.parl_io_conf() #[cfg(soc_has_uart0)]
.modify(|_, w| w.parl_rst_en().set_bit()); Peripheral::Uart0 => {
system system.uart(0).conf().modify(|_, w| w.rst_en().bit(reset));
.parl_io_conf() }
.modify(|_, w| w.parl_rst_en().clear_bit()); #[cfg(soc_has_uart1)]
} Peripheral::Uart1 => {
#[cfg(soc_has_hmac)] system.uart(1).conf().modify(|_, w| w.rst_en().bit(reset));
Peripheral::Hmac => { }
system.hmac_conf().modify(|_, w| w.hmac_rst_en().set_bit()); #[cfg(soc_has_rsa)]
system Peripheral::Rsa => {
.hmac_conf() system.rsa_conf().modify(|_, w| w.rsa_rst_en().bit(reset));
.modify(|_, w| w.hmac_rst_en().clear_bit()); }
} #[cfg(soc_has_parl_io)]
#[cfg(soc_has_ecc)] Peripheral::ParlIo => {
Peripheral::Ecc => { system
system.ecc_conf().modify(|_, w| w.ecc_rst_en().set_bit()); .parl_io_conf()
system.ecc_conf().modify(|_, w| w.ecc_rst_en().clear_bit()); .modify(|_, w| w.parl_rst_en().bit(reset));
} }
#[cfg(soc_has_etm)] #[cfg(soc_has_hmac)]
Peripheral::Etm => { Peripheral::Hmac => {
system.etm_conf().modify(|_, w| w.etm_rst_en().set_bit()); system.hmac_conf().modify(|_, w| w.hmac_rst_en().bit(reset));
system.etm_conf().modify(|_, w| w.etm_rst_en().clear_bit()); }
} #[cfg(soc_has_ecc)]
#[cfg(soc_has_trace0)] Peripheral::Ecc => {
Peripheral::Trace0 => { system.ecc_conf().modify(|_, w| w.ecc_rst_en().bit(reset));
system }
.trace_conf() #[cfg(soc_has_etm)]
.modify(|_, w| w.trace_rst_en().set_bit()); Peripheral::Etm => {
system system.etm_conf().modify(|_, w| w.etm_rst_en().bit(reset));
.trace_conf() }
.modify(|_, w| w.trace_rst_en().clear_bit()); #[cfg(soc_has_trace0)]
} Peripheral::Trace0 => {
#[cfg(soc_has_systimer)] system
Peripheral::Systimer => { .trace_conf()
system .modify(|_, w| w.trace_rst_en().bit(reset));
.systimer_conf() }
.modify(|_, w| w.systimer_rst_en().set_bit()); #[cfg(soc_has_systimer)]
system Peripheral::Systimer => {
.systimer_conf() system
.modify(|_, w| w.systimer_rst_en().clear_bit()); .systimer_conf()
} .modify(|_, w| w.systimer_rst_en().bit(reset));
#[cfg(tsens)] }
Peripheral::Tsens => { #[cfg(tsens)]
system Peripheral::Tsens => {
.tsens_clk_conf() system
.modify(|_, w| w.tsens_rst_en().set_bit()); .tsens_clk_conf()
system .modify(|_, w| w.tsens_rst_en().bit(reset));
.tsens_clk_conf()
.modify(|_, w| w.tsens_rst_en().clear_bit());
}
} }
} }
} }
@ -1134,21 +1004,20 @@ impl PeripheralClockControl {
let mut ref_counts = PERIPHERAL_REF_COUNT.borrow_ref_mut(cs); let mut ref_counts = PERIPHERAL_REF_COUNT.borrow_ref_mut(cs);
let ref_count = &mut ref_counts[peripheral as usize]; let ref_count = &mut ref_counts[peripheral as usize];
if !force { if !force {
let prev = *ref_count;
if enable { if enable {
let prev = *ref_count;
*ref_count += 1; *ref_count += 1;
trace!("Enable {:?} {} -> {}", peripheral, prev, *ref_count); trace!("Enable {:?} {} -> {}", peripheral, prev, *ref_count);
if prev > 0 { if prev > 0 {
return false; return false;
} }
} else { } else {
let prev = *ref_count; assert!(prev != 0);
*ref_count -= 1; *ref_count -= 1;
trace!("Disable {:?} {} -> {}", peripheral, prev, *ref_count); trace!("Disable {:?} {} -> {}", peripheral, prev, *ref_count);
if prev > 1 { if prev > 1 {
return false; return false;
} }
assert!(prev != 0);
}; };
} else if !enable { } else if !enable {
assert!(*ref_count == 0); assert!(*ref_count == 0);