mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-03 15:15:01 +00:00
Separate TIMG into timer0, (timer1), wdt (#104)
* Separate TIMG into timer0, (timer1), wdt * Apply suggestions from code review * Remove left-over code * Ignore settings.json
This commit is contained in:
parent
907d43ed6f
commit
147d8de988
3
.gitignore
vendored
3
.gitignore
vendored
@ -12,3 +12,6 @@ Cargo.lock
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# MSVC Windows builds of rustc generate these, which store debugging information
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# MSVC Windows builds of rustc generate these, which store debugging information
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*.pdb
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*.pdb
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# Other
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**/settings.json
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23
esp-hal-common/.vscode/esp32.settings.json
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23
esp-hal-common/.vscode/esp32.settings.json
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@ -0,0 +1,23 @@
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{
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"rust-analyzer.cargo.features": [
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"esp32"
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],
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"rust-analyzer.cargo.allFeatures": false,
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"editor.formatOnSave": false,
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"rust-analyzer.checkOnSave.allTargets": true,
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"rust-analyzer.checkOnSave.allFeatures": false,
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"rust-analyzer.checkOnSave.overrideCommand": [
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"cargo",
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"check",
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"--features",
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"esp32",
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"--message-format=json",
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"-Z",
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"build-std=core",
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"--target",
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"xtensa-esp32-none-elf",
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"--examples",
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"--lib",
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],
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"rust-analyzer.cargo.buildScripts.enable": false
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}
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23
esp-hal-common/.vscode/esp32s2.settings.json
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23
esp-hal-common/.vscode/esp32s2.settings.json
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@ -0,0 +1,23 @@
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{
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"rust-analyzer.cargo.features": [
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"esp32s2"
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],
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"rust-analyzer.cargo.allFeatures": false,
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"editor.formatOnSave": false,
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"rust-analyzer.checkOnSave.allTargets": true,
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"rust-analyzer.checkOnSave.allFeatures": false,
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"rust-analyzer.checkOnSave.overrideCommand": [
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"cargo",
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"check",
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"--features",
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"esp32s2",
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"--message-format=json",
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"-Z",
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"build-std=core",
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"--target",
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"xtensa-esp32s2-none-elf",
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"--examples",
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"--lib",
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],
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"rust-analyzer.cargo.buildScripts.enable": false
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}
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23
esp-hal-common/.vscode/esp32s3.settings.json
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23
esp-hal-common/.vscode/esp32s3.settings.json
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@ -0,0 +1,23 @@
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{
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"rust-analyzer.cargo.features": [
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"esp32s3"
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],
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"rust-analyzer.cargo.allFeatures": false,
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"editor.formatOnSave": false,
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"rust-analyzer.checkOnSave.allTargets": true,
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"rust-analyzer.checkOnSave.allFeatures": false,
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"rust-analyzer.checkOnSave.overrideCommand": [
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"cargo",
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"check",
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"--features",
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"esp32s3",
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"--message-format=json",
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"-Z",
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"build-std=core",
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"--target",
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"xtensa-esp32s3-none-elf",
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"--examples",
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"--lib",
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],
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"rust-analyzer.cargo.buildScripts.enable": false
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}
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@ -41,10 +41,10 @@ smart-leds-trait = { version = "0.2.1", optional = true }
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#
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#
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# Please note: for now we use git-dependencies from the `with_source` branch however we pin the dependency
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# Please note: for now we use git-dependencies from the `with_source` branch however we pin the dependency
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# to specific commits.
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# to specific commits.
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esp32_pac = { package = "esp32", git = "https://github.com/esp-rs/esp-pacs.git", rev = "f5905f30f4796ed4da8fe333b6ed9700901c515b", optional = true }
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esp32_pac = { package = "esp32", git = "https://github.com/esp-rs/esp-pacs.git", rev = "148dbb843cba3c311364aa994b8f3f773d15b04f", optional = true }
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esp32c3_pac = { package = "esp32c3", git = "https://github.com/esp-rs/esp-pacs.git", rev = "f5905f30f4796ed4da8fe333b6ed9700901c515b", optional = true }
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esp32c3_pac = { package = "esp32c3", git = "https://github.com/esp-rs/esp-pacs.git", rev = "148dbb843cba3c311364aa994b8f3f773d15b04f", optional = true }
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esp32s2_pac = { package = "esp32s2", git = "https://github.com/esp-rs/esp-pacs.git", rev = "f5905f30f4796ed4da8fe333b6ed9700901c515b", optional = true }
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esp32s2_pac = { package = "esp32s2", git = "https://github.com/esp-rs/esp-pacs.git", rev = "148dbb843cba3c311364aa994b8f3f773d15b04f", optional = true }
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esp32s3_pac = { package = "esp32s3", git = "https://github.com/esp-rs/esp-pacs.git", rev = "f5905f30f4796ed4da8fe333b6ed9700901c515b", optional = true }
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esp32s3_pac = { package = "esp32s3", git = "https://github.com/esp-rs/esp-pacs.git", rev = "148dbb843cba3c311364aa994b8f3f773d15b04f", optional = true }
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[features]
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[features]
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esp32 = [ "esp32_pac/rt", "xtensa", "dual_core", "xtensa-lx-rt/esp32", "xtensa-lx/esp32", "smartled"]
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esp32 = [ "esp32_pac/rt", "xtensa", "dual_core", "xtensa-lx-rt/esp32", "xtensa-lx/esp32", "smartled"]
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@ -1,13 +1,18 @@
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//! General-purpose timers
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//! General-purpose timers
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use core::marker::PhantomData;
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use embedded_hal::{
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use embedded_hal::{
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timer::{Cancel, CountDown, Periodic},
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timer::{Cancel, CountDown, Periodic},
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watchdog::WatchdogDisable,
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watchdog::{Watchdog, WatchdogDisable, WatchdogEnable},
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};
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};
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use fugit::{MegahertzU32, MicrosDurationU64};
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use fugit::{MegahertzU32, MicrosDurationU64};
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use void::Void;
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use void::Void;
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use crate::pac::{timg0::RegisterBlock, TIMG0, TIMG1};
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use crate::{
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clock::Clocks,
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pac::{timg0::RegisterBlock, TIMG0, TIMG1},
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};
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/// Custom timer error type
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/// Custom timer error type
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#[derive(Debug)]
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#[derive(Debug)]
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@ -17,6 +22,67 @@ pub enum Error {
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AlarmInactive,
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AlarmInactive,
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}
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}
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// A timergroup consisting of up to 2 timers (chip dependent) and a watchdog
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// timer
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pub struct TimerGroup<T>
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where
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T: TimerGroupInstance,
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{
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pub timer0: Timer<Timer0<T>>,
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#[cfg(not(feature = "esp32c3"))]
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pub timer1: Timer<Timer1<T>>,
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pub wdt: Wdt<T>,
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}
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pub trait TimerGroupInstance {
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fn register_block() -> *const RegisterBlock;
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}
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impl TimerGroupInstance for TIMG0 {
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#[inline(always)]
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fn register_block() -> *const RegisterBlock {
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crate::pac::TIMG0::PTR
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}
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}
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impl TimerGroupInstance for TIMG1 {
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#[inline(always)]
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fn register_block() -> *const RegisterBlock {
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crate::pac::TIMG1::PTR
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}
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}
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impl<T> TimerGroup<T>
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where
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T: TimerGroupInstance,
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{
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pub fn new(_timer_group: T, clocks: &Clocks) -> Self {
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let timer0 = Timer::new(
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Timer0 {
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phantom: PhantomData::default(),
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},
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clocks.apb_clock,
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);
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#[cfg(not(feature = "esp32c3"))]
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let timer1 = Timer::new(
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Timer1 {
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phantom: PhantomData::default(),
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},
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clocks.apb_clock,
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);
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let wdt = Wdt::new();
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Self {
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timer0,
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#[cfg(not(feature = "esp32c3"))]
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timer1,
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wdt,
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}
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}
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}
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/// General-purpose timer
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/// General-purpose timer
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pub struct Timer<T> {
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pub struct Timer<T> {
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timg: T,
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timg: T,
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@ -50,11 +116,16 @@ where
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self.timg.unlisten();
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self.timg.unlisten();
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}
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}
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/// Clear intterupt status
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/// Clear interrupt status
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pub fn clear_interrupt(&mut self) {
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pub fn clear_interrupt(&mut self) {
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self.timg.clear_interrupt();
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self.timg.clear_interrupt();
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}
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}
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/// Check if the interrupt is asserted
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pub fn is_interrupt_set(&self) -> bool {
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self.timg.is_interrupt_set()
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}
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/// Read current raw timer value in timer ticks
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/// Read current raw timer value in timer ticks
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pub fn read_raw(&self) -> u64 {
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pub fn read_raw(&self) -> u64 {
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self.timg.read_raw()
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self.timg.read_raw()
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@ -63,56 +134,92 @@ where
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/// Timer peripheral instance
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/// Timer peripheral instance
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pub trait Instance {
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pub trait Instance {
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fn register_block(&self) -> &RegisterBlock;
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fn reset_counter(&mut self);
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fn set_counter_active(&mut self, state: bool);
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fn is_counter_active(&self) -> bool;
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fn set_counter_decrementing(&mut self, decrementing: bool);
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fn set_auto_reload(&mut self, auto_reload: bool);
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fn set_alarm_active(&mut self, state: bool);
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fn is_alarm_active(&self) -> bool;
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fn load_alarm_value(&mut self, value: u64);
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fn listen(&mut self);
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fn unlisten(&mut self);
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fn clear_interrupt(&mut self);
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fn read_raw(&self) -> u64;
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fn divider(&self) -> u32;
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fn is_interrupt_set(&self) -> bool;
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}
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pub struct Timer0<TG> {
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phantom: PhantomData<TG>,
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}
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/// Timer peripheral instance
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impl<TG> Instance for Timer0<TG>
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where
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TG: TimerGroupInstance,
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{
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fn reset_counter(&mut self) {
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fn reset_counter(&mut self) {
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let reg_block = self.register_block();
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let reg_block = unsafe { &*TG::register_block() };
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reg_block
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reg_block.t0loadlo.write(|w| unsafe { w.load_lo().bits(0) });
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.t0loadlo
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.write(|w| unsafe { w.t0_load_lo().bits(0) });
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reg_block
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reg_block.t0loadhi.write(|w| unsafe { w.load_hi().bits(0) });
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.t0loadhi
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.write(|w| unsafe { w.t0_load_hi().bits(0) });
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reg_block.t0load.write(|w| unsafe { w.t0_load().bits(1) });
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reg_block.t0load.write(|w| unsafe { w.load().bits(1) });
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}
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}
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fn set_counter_active(&mut self, state: bool) {
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fn set_counter_active(&mut self, state: bool) {
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self.register_block()
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let reg_block = unsafe { &*TG::register_block() };
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.t0config
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.modify(|_, w| w.t0_en().bit(state));
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reg_block.t0config.modify(|_, w| w.en().bit(state));
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}
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}
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fn is_counter_active(&self) -> bool {
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fn is_counter_active(&self) -> bool {
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self.register_block().t0config.read().t0_en().bit_is_set()
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let reg_block = unsafe { &*TG::register_block() };
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reg_block.t0config.read().en().bit_is_set()
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}
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}
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fn set_counter_decrementing(&mut self, decrementing: bool) {
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fn set_counter_decrementing(&mut self, decrementing: bool) {
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self.register_block()
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let reg_block = unsafe { &*TG::register_block() };
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reg_block
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.t0config
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.t0config
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.modify(|_, w| w.t0_increase().bit(!decrementing));
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.modify(|_, w| w.increase().bit(!decrementing));
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}
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}
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fn set_auto_reload(&mut self, auto_reload: bool) {
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fn set_auto_reload(&mut self, auto_reload: bool) {
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self.register_block()
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let reg_block = unsafe { &*TG::register_block() };
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reg_block
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.t0config
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.t0config
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.modify(|_, w| w.t0_autoreload().bit(auto_reload));
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.modify(|_, w| w.autoreload().bit(auto_reload));
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}
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}
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fn set_alarm_active(&mut self, state: bool) {
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fn set_alarm_active(&mut self, state: bool) {
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self.register_block()
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let reg_block = unsafe { &*TG::register_block() };
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.t0config
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.modify(|_, w| w.t0_alarm_en().bit(state));
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reg_block.t0config.modify(|_, w| w.alarm_en().bit(state));
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}
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}
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fn is_alarm_active(&self) -> bool {
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fn is_alarm_active(&self) -> bool {
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self.register_block()
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let reg_block = unsafe { &*TG::register_block() };
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.t0config
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.read()
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reg_block.t0config.read().alarm_en().bit_is_set()
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.t0_alarm_en()
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.bit_is_set()
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}
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}
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fn load_alarm_value(&mut self, value: u64) {
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fn load_alarm_value(&mut self, value: u64) {
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@ -120,96 +227,211 @@ pub trait Instance {
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let high = (value >> 32) as u32;
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let high = (value >> 32) as u32;
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let low = (value & 0xFFFF_FFFF) as u32;
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let low = (value & 0xFFFF_FFFF) as u32;
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|
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let reg_block = self.register_block();
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let reg_block = unsafe { &*TG::register_block() };
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reg_block
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reg_block
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.t0alarmlo
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.t0alarmlo
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.write(|w| unsafe { w.t0_alarm_lo().bits(low) });
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.write(|w| unsafe { w.alarm_lo().bits(low) });
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reg_block
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reg_block
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.t0alarmhi
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.t0alarmhi
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.write(|w| unsafe { w.t0_alarm_hi().bits(high) });
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.write(|w| unsafe { w.alarm_hi().bits(high) });
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}
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fn set_wdt_enabled(&mut self, enabled: bool) {
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let reg_block = self.register_block();
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reg_block
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.wdtwprotect
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.write(|w| unsafe { w.wdt_wkey().bits(0x50D8_3AA1u32) });
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|
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if !enabled {
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reg_block.wdtconfig0.write(|w| unsafe { w.bits(0) });
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} else {
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reg_block.wdtconfig0.write(|w| w.wdt_en().bit(true));
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}
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|
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reg_block
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.wdtwprotect
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.write(|w| unsafe { w.wdt_wkey().bits(0u32) });
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}
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}
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|
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fn listen(&mut self) {
|
fn listen(&mut self) {
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let reg_block = unsafe { &*TG::register_block() };
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|
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// always use level interrupt
|
// always use level interrupt
|
||||||
#[cfg(any(feature = "esp32", feature = "esp32s2"))]
|
#[cfg(any(feature = "esp32", feature = "esp32s2"))]
|
||||||
self.register_block()
|
reg_block.t0config.modify(|_, w| w.level_int_en().set_bit());
|
||||||
.t0config
|
|
||||||
.modify(|_, w| w.t0_level_int_en().set_bit());
|
|
||||||
|
|
||||||
self.register_block()
|
reg_block
|
||||||
.int_ena_timers
|
.int_ena_timers
|
||||||
.modify(|_, w| w.t0_int_ena().set_bit());
|
.modify(|_, w| w.t0_int_ena().set_bit());
|
||||||
}
|
}
|
||||||
|
|
||||||
fn unlisten(&mut self) {
|
fn unlisten(&mut self) {
|
||||||
self.register_block()
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
.int_ena_timers
|
.int_ena_timers
|
||||||
.modify(|_, w| w.t0_int_ena().clear_bit());
|
.modify(|_, w| w.t0_int_ena().clear_bit());
|
||||||
}
|
}
|
||||||
|
|
||||||
fn clear_interrupt(&mut self) {
|
fn clear_interrupt(&mut self) {
|
||||||
self.register_block()
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
.int_clr_timers
|
|
||||||
.write(|w| w.t0_int_clr().set_bit());
|
reg_block.int_clr_timers.write(|w| w.t0_int_clr().set_bit());
|
||||||
}
|
}
|
||||||
|
|
||||||
fn read_raw(&self) -> u64 {
|
fn read_raw(&self) -> u64 {
|
||||||
self.register_block()
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
.t0update
|
|
||||||
.write(|w| unsafe { w.bits(0) });
|
|
||||||
|
|
||||||
let value_lo = self.register_block().t0lo.read().bits() as u64;
|
reg_block.t0update.write(|w| unsafe { w.bits(0) });
|
||||||
let value_hi = (self.register_block().t0hi.read().bits() as u64) << 32;
|
|
||||||
|
let value_lo = reg_block.t0lo.read().bits() as u64;
|
||||||
|
let value_hi = (reg_block.t0hi.read().bits() as u64) << 32;
|
||||||
|
|
||||||
(value_lo | value_hi) as u64
|
(value_lo | value_hi) as u64
|
||||||
}
|
}
|
||||||
|
|
||||||
fn divider(&self) -> u32 {
|
fn divider(&self) -> u32 {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
// From the ESP32 TRM, "11.2.1 16-bit Prescaler and Clock Selection":
|
// From the ESP32 TRM, "11.2.1 16-bit Prescaler and Clock Selection":
|
||||||
//
|
//
|
||||||
// "The prescaler can divide the APB clock by a factor from 2 to 65536.
|
// "The prescaler can divide the APB clock by a factor from 2 to 65536.
|
||||||
// Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2;
|
// Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2;
|
||||||
// when TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will
|
// when TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will
|
||||||
// cause the clock to be divided by exactly that value."
|
// cause the clock to be divided by exactly that value."
|
||||||
match self.register_block().t0config.read().t0_divider().bits() {
|
match reg_block.t0config.read().divider().bits() {
|
||||||
0 => 65536,
|
0 => 65536,
|
||||||
1 | 2 => 2,
|
1 | 2 => 2,
|
||||||
n => n as u32,
|
n => n as u32,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
|
||||||
|
|
||||||
impl Instance for TIMG0 {
|
fn is_interrupt_set(&self) -> bool {
|
||||||
#[inline(always)]
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
fn register_block(&self) -> &RegisterBlock {
|
|
||||||
self
|
reg_block.int_raw_timers.read().t0_int_raw().bit_is_set()
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
impl Instance for TIMG1 {
|
#[cfg(not(feature = "esp32c3"))]
|
||||||
#[inline(always)]
|
pub struct Timer1<TG> {
|
||||||
fn register_block(&self) -> &RegisterBlock {
|
phantom: PhantomData<TG>,
|
||||||
self
|
}
|
||||||
|
|
||||||
|
/// Timer peripheral instance
|
||||||
|
#[cfg(not(feature = "esp32c3"))]
|
||||||
|
impl<TG> Instance for Timer1<TG>
|
||||||
|
where
|
||||||
|
TG: TimerGroupInstance,
|
||||||
|
{
|
||||||
|
fn reset_counter(&mut self) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.t1loadlo.write(|w| unsafe { w.load_lo().bits(0) });
|
||||||
|
|
||||||
|
reg_block.t1loadhi.write(|w| unsafe { w.load_hi().bits(0) });
|
||||||
|
|
||||||
|
reg_block.t1load.write(|w| unsafe { w.load().bits(1) });
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_counter_active(&mut self, state: bool) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.t1config.modify(|_, w| w.en().bit(state));
|
||||||
|
}
|
||||||
|
|
||||||
|
fn is_counter_active(&self) -> bool {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.t1config.read().en().bit_is_set()
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_counter_decrementing(&mut self, decrementing: bool) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.t1config
|
||||||
|
.modify(|_, w| w.increase().bit(!decrementing));
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_auto_reload(&mut self, auto_reload: bool) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.t1config
|
||||||
|
.modify(|_, w| w.autoreload().bit(auto_reload));
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_alarm_active(&mut self, state: bool) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.t1config.modify(|_, w| w.alarm_en().bit(state));
|
||||||
|
}
|
||||||
|
|
||||||
|
fn is_alarm_active(&self) -> bool {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.t1config.read().alarm_en().bit_is_set()
|
||||||
|
}
|
||||||
|
|
||||||
|
fn load_alarm_value(&mut self, value: u64) {
|
||||||
|
let value = value & 0x3F_FFFF_FFFF_FFFF;
|
||||||
|
let high = (value >> 32) as u32;
|
||||||
|
let low = (value & 0xFFFF_FFFF) as u32;
|
||||||
|
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.t1alarmlo
|
||||||
|
.write(|w| unsafe { w.alarm_lo().bits(low) });
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.t1alarmhi
|
||||||
|
.write(|w| unsafe { w.alarm_hi().bits(high) });
|
||||||
|
}
|
||||||
|
|
||||||
|
fn listen(&mut self) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
// always use level interrupt
|
||||||
|
#[cfg(any(feature = "esp32", feature = "esp32s2"))]
|
||||||
|
reg_block.t1config.modify(|_, w| w.level_int_en().set_bit());
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.int_ena_timers
|
||||||
|
.modify(|_, w| w.t1_int_ena().set_bit());
|
||||||
|
}
|
||||||
|
|
||||||
|
fn unlisten(&mut self) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.int_ena_timers
|
||||||
|
.modify(|_, w| w.t1_int_ena().clear_bit());
|
||||||
|
}
|
||||||
|
|
||||||
|
fn clear_interrupt(&mut self) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.int_clr_timers.write(|w| w.t1_int_clr().set_bit());
|
||||||
|
}
|
||||||
|
|
||||||
|
fn read_raw(&self) -> u64 {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.t1update.write(|w| unsafe { w.bits(0) });
|
||||||
|
|
||||||
|
let value_lo = reg_block.t1lo.read().bits() as u64;
|
||||||
|
let value_hi = (reg_block.t1hi.read().bits() as u64) << 32;
|
||||||
|
|
||||||
|
(value_lo | value_hi) as u64
|
||||||
|
}
|
||||||
|
|
||||||
|
fn divider(&self) -> u32 {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
// From the ESP32 TRM, "11.2.1 16-bit Prescaler and Clock Selection":
|
||||||
|
//
|
||||||
|
// "The prescaler can divide the APB clock by a factor from 2 to 65536.
|
||||||
|
// Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2;
|
||||||
|
// when TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will
|
||||||
|
// cause the clock to be divided by exactly that value."
|
||||||
|
match reg_block.t1config.read().divider().bits() {
|
||||||
|
0 => 65536,
|
||||||
|
1 | 2 => 2,
|
||||||
|
n => n as u32,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn is_interrupt_set(&self) -> bool {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block.int_raw_timers.read().t1_int_raw().bit_is_set()
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -261,10 +483,8 @@ where
|
|||||||
panic!("Called wait on an inactive timer!")
|
panic!("Called wait on an inactive timer!")
|
||||||
}
|
}
|
||||||
|
|
||||||
let reg_block = self.timg.register_block();
|
if self.timg.is_interrupt_set() {
|
||||||
|
self.timg.clear_interrupt();
|
||||||
if reg_block.int_raw_timers.read().t0_int_raw().bit_is_set() {
|
|
||||||
reg_block.int_clr_timers.write(|w| w.t0_int_clr().set_bit());
|
|
||||||
self.timg.set_alarm_active(true);
|
self.timg.set_alarm_active(true);
|
||||||
|
|
||||||
Ok(())
|
Ok(())
|
||||||
@ -295,11 +515,128 @@ where
|
|||||||
|
|
||||||
impl<T> Periodic for Timer<T> where T: Instance {}
|
impl<T> Periodic for Timer<T> where T: Instance {}
|
||||||
|
|
||||||
impl<T> WatchdogDisable for Timer<T>
|
/// Watchdog timer
|
||||||
|
pub struct Wdt<TG> {
|
||||||
|
phantom: PhantomData<TG>,
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Watchdog driver
|
||||||
|
impl<TG> Wdt<TG>
|
||||||
where
|
where
|
||||||
T: Instance,
|
TG: TimerGroupInstance,
|
||||||
{
|
{
|
||||||
fn disable(&mut self) {
|
/// Create a new watchdog timer instance
|
||||||
self.timg.set_wdt_enabled(false);
|
pub fn new() -> Self {
|
||||||
|
Self {
|
||||||
|
phantom: PhantomData::default(),
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_wdt_enabled(&mut self, enabled: bool) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtwprotect
|
||||||
|
.write(|w| unsafe { w.wdt_wkey().bits(0x50D8_3AA1u32) });
|
||||||
|
|
||||||
|
if !enabled {
|
||||||
|
reg_block.wdtconfig0.write(|w| unsafe { w.bits(0) });
|
||||||
|
} else {
|
||||||
|
reg_block.wdtconfig0.write(|w| w.wdt_en().bit(true));
|
||||||
|
}
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtwprotect
|
||||||
|
.write(|w| unsafe { w.wdt_wkey().bits(0u32) });
|
||||||
|
}
|
||||||
|
|
||||||
|
fn feed(&mut self) {
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtwprotect
|
||||||
|
.write(|w| unsafe { w.wdt_wkey().bits(0x50D8_3AA1u32) });
|
||||||
|
|
||||||
|
reg_block.wdtfeed.write(|w| unsafe { w.bits(1) });
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtwprotect
|
||||||
|
.write(|w| unsafe { w.wdt_wkey().bits(0u32) });
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_timeout(&mut self, timeout: MicrosDurationU64) {
|
||||||
|
let timeout_raw = (timeout.to_nanos() * 10 / 125) as u32;
|
||||||
|
|
||||||
|
let reg_block = unsafe { &*TG::register_block() };
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtwprotect
|
||||||
|
.write(|w| unsafe { w.wdt_wkey().bits(0x50D8_3AA1u32) });
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtconfig1
|
||||||
|
.write(|w| unsafe { w.wdt_clk_prescale().bits(1) });
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtconfig2
|
||||||
|
.write(|w| unsafe { w.wdt_stg0_hold().bits(timeout_raw) });
|
||||||
|
|
||||||
|
reg_block.wdtconfig0.write(|w| unsafe {
|
||||||
|
w.wdt_en()
|
||||||
|
.bit(true)
|
||||||
|
.wdt_stg0()
|
||||||
|
.bits(3)
|
||||||
|
.wdt_cpu_reset_length()
|
||||||
|
.bits(1)
|
||||||
|
.wdt_sys_reset_length()
|
||||||
|
.bits(1)
|
||||||
|
.wdt_stg1()
|
||||||
|
.bits(0)
|
||||||
|
.wdt_stg2()
|
||||||
|
.bits(0)
|
||||||
|
.wdt_stg3()
|
||||||
|
.bits(0)
|
||||||
|
});
|
||||||
|
|
||||||
|
#[cfg(feature = "esp32c3")]
|
||||||
|
reg_block
|
||||||
|
.wdtconfig0
|
||||||
|
.modify(|_, w| w.wdt_conf_update_en().set_bit());
|
||||||
|
|
||||||
|
reg_block
|
||||||
|
.wdtwprotect
|
||||||
|
.write(|w| unsafe { w.wdt_wkey().bits(0u32) });
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<TG> WatchdogDisable for Wdt<TG>
|
||||||
|
where
|
||||||
|
TG: TimerGroupInstance,
|
||||||
|
{
|
||||||
|
fn disable(&mut self) {
|
||||||
|
self.set_wdt_enabled(false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<TG> WatchdogEnable for Wdt<TG>
|
||||||
|
where
|
||||||
|
TG: TimerGroupInstance,
|
||||||
|
{
|
||||||
|
type Time = MicrosDurationU64;
|
||||||
|
|
||||||
|
fn start<T>(&mut self, period: T)
|
||||||
|
where
|
||||||
|
T: Into<Self::Time>,
|
||||||
|
{
|
||||||
|
self.set_timeout(period.into());
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<TG> Watchdog for Wdt<TG>
|
||||||
|
where
|
||||||
|
TG: TimerGroupInstance,
|
||||||
|
{
|
||||||
|
fn feed(&mut self) {
|
||||||
|
self.feed();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -11,9 +11,9 @@ use esp32_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -25,11 +25,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -15,10 +15,10 @@ use esp32_hal::{
|
|||||||
config::{Config, DataBits, Parity, StopBits},
|
config::{Config, DataBits, Parity, StopBits},
|
||||||
TxRxPins,
|
TxRxPins,
|
||||||
},
|
},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use nb::block;
|
use nb::block;
|
||||||
@ -31,11 +31,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let config = Config {
|
let config = Config {
|
||||||
|
@ -6,9 +6,9 @@ use esp32_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -19,11 +19,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Set GPIO15 as an output, and set its state high initially.
|
// Set GPIO15 as an output, and set its state high initially.
|
||||||
|
@ -11,9 +11,9 @@ use esp32_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -24,11 +24,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -10,11 +10,11 @@ use esp32_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
||||||
@ -31,13 +31,15 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Set GPIO15 as an output, and set its state high initially.
|
// Set GPIO15 as an output, and set its state high initially.
|
||||||
|
@ -17,11 +17,11 @@ use esp32_hal::{
|
|||||||
clock::ClockControl,
|
clock::ClockControl,
|
||||||
pac,
|
pac,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
utils::{smartLedAdapter, SmartLedsAdapter},
|
utils::{smartLedAdapter, SmartLedsAdapter},
|
||||||
Delay,
|
Delay,
|
||||||
PulseControl,
|
PulseControl,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
IO,
|
IO,
|
||||||
};
|
};
|
||||||
#[allow(unused_imports)]
|
#[allow(unused_imports)]
|
||||||
@ -41,11 +41,12 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Configure RMT peripheral globally
|
// Configure RMT peripheral globally
|
||||||
|
@ -3,7 +3,14 @@
|
|||||||
|
|
||||||
use core::fmt::Write;
|
use core::fmt::Write;
|
||||||
|
|
||||||
use esp32_hal::{clock::ClockControl, pac::Peripherals, prelude::*, RtcCntl, Serial, Timer};
|
use esp32_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -14,12 +21,14 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
timer0.start(1u64.secs());
|
timer0.start(1u64.secs());
|
||||||
|
@ -27,9 +27,9 @@ use esp32_hal::{
|
|||||||
i2c::I2C,
|
i2c::I2C,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -42,12 +42,14 @@ fn main() -> ! {
|
|||||||
let mut system = peripherals.DPORT.split();
|
let mut system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable watchdog timer
|
// Disable watchdog timer
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -7,10 +7,11 @@ use esp32_hal::{
|
|||||||
clock::ClockControl,
|
clock::ClockControl,
|
||||||
pac::{Peripherals, TIMG1},
|
pac::{Peripherals, TIMG1},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::{Timer0, TimerGroup},
|
||||||
CpuControl,
|
CpuControl,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
use esp_hal_common::Timer;
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -27,13 +28,19 @@ fn _main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut timer1 = timer_group1.timer0;
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
timer0.start(1u64.secs());
|
timer0.start(1u64.secs());
|
||||||
@ -55,7 +62,10 @@ fn _main() -> ! {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn cpu1_task(timer: &mut Timer<TIMG1>, counter: &xtensa_lx::mutex::SpinLockMutex<AtomicI32>) -> ! {
|
fn cpu1_task(
|
||||||
|
timer: &mut Timer<Timer0<TIMG1>>,
|
||||||
|
counter: &xtensa_lx::mutex::SpinLockMutex<AtomicI32>,
|
||||||
|
) -> ! {
|
||||||
println!("Hello World - Core 1!");
|
println!("Hello World - Core 1!");
|
||||||
loop {
|
loop {
|
||||||
block!(timer.wait()).unwrap();
|
block!(timer.wait()).unwrap();
|
||||||
|
@ -8,8 +8,8 @@ use esp32_hal::{
|
|||||||
pac::{Peripherals, UART0},
|
pac::{Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
ram,
|
ram,
|
||||||
|
timer::TimerGroup,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -30,11 +30,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT flash boot protection
|
// Disable MWDT flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
// The RWDT flash boot protection remains enabled and it being triggered is part
|
// The RWDT flash boot protection remains enabled and it being triggered is part
|
||||||
// of the example
|
// of the example
|
||||||
|
|
||||||
|
@ -8,9 +8,9 @@ use esp32_hal::{
|
|||||||
efuse::Efuse,
|
efuse::Efuse,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -21,12 +21,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.DPORT.split();
|
let system = peripherals.DPORT.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
||||||
|
@ -13,10 +13,10 @@ use esp32_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
serial::config::AtCmdConfig,
|
serial::config::AtCmdConfig,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -33,14 +33,19 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
||||||
|
@ -24,10 +24,10 @@ use esp32_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
spi::{Spi, SpiMode},
|
spi::{Spi, SpiMode},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -41,10 +41,11 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -8,20 +8,25 @@ use esp32_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::{Timer0, Timer1, TimerGroup},
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
use esp_hal_common::Timer;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
|
|
||||||
static mut SERIAL: SpinLockMutex<RefCell<Option<Serial<UART0>>>> =
|
static mut SERIAL: SpinLockMutex<RefCell<Option<Serial<UART0>>>> =
|
||||||
SpinLockMutex::new(RefCell::new(None));
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
static mut TIMER0: SpinLockMutex<RefCell<Option<Timer<TIMG0>>>> =
|
static mut TIMER00: SpinLockMutex<RefCell<Option<Timer<Timer0<TIMG0>>>>> =
|
||||||
SpinLockMutex::new(RefCell::new(None));
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
static mut TIMER1: SpinLockMutex<RefCell<Option<Timer<TIMG1>>>> =
|
static mut TIMER01: SpinLockMutex<RefCell<Option<Timer<Timer1<TIMG0>>>>> =
|
||||||
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
|
static mut TIMER10: SpinLockMutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> =
|
||||||
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
|
static mut TIMER11: SpinLockMutex<RefCell<Option<Timer<Timer1<TIMG1>>>>> =
|
||||||
SpinLockMutex::new(RefCell::new(None));
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
|
|
||||||
#[entry]
|
#[entry]
|
||||||
@ -31,14 +36,22 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer00 = timer_group0.timer0;
|
||||||
|
let mut timer01 = timer_group0.timer1;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut timer10 = timer_group1.timer0;
|
||||||
|
let mut timer11 = timer_group1.timer1;
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
@ -46,21 +59,37 @@ fn main() -> ! {
|
|||||||
pac::Interrupt::TG0_T0_LEVEL,
|
pac::Interrupt::TG0_T0_LEVEL,
|
||||||
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
);
|
);
|
||||||
timer0.start(500u64.millis());
|
interrupt::enable(
|
||||||
timer0.listen();
|
Cpu::ProCpu,
|
||||||
|
pac::Interrupt::TG0_T1_LEVEL,
|
||||||
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
|
);
|
||||||
|
timer00.start(500u64.millis());
|
||||||
|
timer00.listen();
|
||||||
|
timer01.start(2500u64.millis());
|
||||||
|
timer01.listen();
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
pac::Interrupt::TG1_T0_LEVEL,
|
pac::Interrupt::TG1_T0_LEVEL,
|
||||||
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
);
|
);
|
||||||
timer1.start(1u64.secs());
|
interrupt::enable(
|
||||||
timer1.listen();
|
Cpu::ProCpu,
|
||||||
|
pac::Interrupt::TG1_T1_LEVEL,
|
||||||
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
|
);
|
||||||
|
timer10.start(1u64.secs());
|
||||||
|
timer10.listen();
|
||||||
|
timer11.start(3u64.secs());
|
||||||
|
timer11.listen();
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&SERIAL).lock(|data| (*data).replace(Some(serial0)));
|
(&SERIAL).lock(|data| (*data).replace(Some(serial0)));
|
||||||
(&TIMER0).lock(|data| (*data).replace(Some(timer0)));
|
(&TIMER00).lock(|data| (*data).replace(Some(timer00)));
|
||||||
(&TIMER1).lock(|data| (*data).replace(Some(timer1)));
|
(&TIMER01).lock(|data| (*data).replace(Some(timer01)));
|
||||||
|
(&TIMER10).lock(|data| (*data).replace(Some(timer10)));
|
||||||
|
(&TIMER11).lock(|data| (*data).replace(Some(timer11)));
|
||||||
}
|
}
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
@ -74,50 +103,84 @@ fn main() -> ! {
|
|||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn level2_interrupt() {
|
pub fn level2_interrupt() {
|
||||||
unsafe {
|
|
||||||
(&SERIAL).lock(|data| {
|
|
||||||
let mut serial = data.borrow_mut();
|
|
||||||
let serial = serial.as_mut().unwrap();
|
|
||||||
writeln!(serial, "Interrupt Level 2").ok();
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
interrupt::clear(
|
interrupt::clear(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
);
|
);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&TIMER0).lock(|data| {
|
(&TIMER00).lock(|data| {
|
||||||
let mut timer0 = data.borrow_mut();
|
let mut timer = data.borrow_mut();
|
||||||
let timer0 = timer0.as_mut().unwrap();
|
let timer = timer.as_mut().unwrap();
|
||||||
timer0.clear_interrupt();
|
|
||||||
timer0.start(500u64.millis());
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(500u64.millis());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 2 - Timer0").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
|
});
|
||||||
|
|
||||||
|
(&TIMER01).lock(|data| {
|
||||||
|
let mut timer = data.borrow_mut();
|
||||||
|
let timer = timer.as_mut().unwrap();
|
||||||
|
|
||||||
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(2500u64.millis());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 2 - Timer1").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn level3_interrupt() {
|
pub fn level3_interrupt() {
|
||||||
unsafe {
|
|
||||||
(&SERIAL).lock(|data| {
|
|
||||||
let mut serial = data.borrow_mut();
|
|
||||||
let serial = serial.as_mut().unwrap();
|
|
||||||
writeln!(serial, "Interrupt Level 3").ok();
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
interrupt::clear(
|
interrupt::clear(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
);
|
);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&TIMER1).lock(|data| {
|
(&TIMER10).lock(|data| {
|
||||||
let mut timer1 = data.borrow_mut();
|
let mut timer = data.borrow_mut();
|
||||||
let timer1 = timer1.as_mut().unwrap();
|
let timer = timer.as_mut().unwrap();
|
||||||
timer1.clear_interrupt();
|
|
||||||
timer1.start(1u64.secs());
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(1u64.secs());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 3 - Timer0").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
|
});
|
||||||
|
|
||||||
|
(&TIMER11).lock(|data| {
|
||||||
|
let mut timer = data.borrow_mut();
|
||||||
|
let timer = timer.as_mut().unwrap();
|
||||||
|
|
||||||
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(3u64.secs());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 3 - Timer1").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
44
esp32-hal/examples/watchdog.rs
Normal file
44
esp32-hal/examples/watchdog.rs
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
//! This demos the watchdog timer.
|
||||||
|
//! Basically the same as `hello_world` but if you remove the call to
|
||||||
|
//! `wdt.feed()` the watchdog will reset the system.
|
||||||
|
|
||||||
|
#![no_std]
|
||||||
|
#![no_main]
|
||||||
|
|
||||||
|
use core::fmt::Write;
|
||||||
|
|
||||||
|
use esp32_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
|
use nb::block;
|
||||||
|
use panic_halt as _;
|
||||||
|
use xtensa_lx_rt::entry;
|
||||||
|
|
||||||
|
#[entry]
|
||||||
|
fn main() -> ! {
|
||||||
|
let peripherals = Peripherals::take().unwrap();
|
||||||
|
let system = peripherals.DPORT.split();
|
||||||
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
|
wdt.start(2u64.secs());
|
||||||
|
timer0.start(1u64.secs());
|
||||||
|
|
||||||
|
loop {
|
||||||
|
wdt.feed();
|
||||||
|
writeln!(serial0, "Hello world!").unwrap();
|
||||||
|
block!(timer0.wait()).unwrap();
|
||||||
|
}
|
||||||
|
}
|
@ -14,6 +14,7 @@ pub use esp_hal_common::{
|
|||||||
ram,
|
ram,
|
||||||
serial,
|
serial,
|
||||||
spi,
|
spi,
|
||||||
|
timer,
|
||||||
utils,
|
utils,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
@ -21,7 +22,6 @@ pub use esp_hal_common::{
|
|||||||
Rng,
|
Rng,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pub use self::gpio::IO;
|
pub use self::gpio::IO;
|
||||||
|
@ -13,9 +13,9 @@ use esp32c3_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
system::SystemExt,
|
system::SystemExt,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -30,13 +30,15 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
let mut pin = io.pins.gpio2.into_analog();
|
let mut pin = io.pins.gpio2.into_analog();
|
||||||
|
@ -14,9 +14,9 @@ use esp32c3_hal::{
|
|||||||
config::{Config, DataBits, Parity, StopBits},
|
config::{Config, DataBits, Parity, StopBits},
|
||||||
TxRxPins,
|
TxRxPins,
|
||||||
},
|
},
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
IO,
|
IO,
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
@ -31,14 +31,17 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
// Disable watchdog timers
|
// Disable watchdog timers
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
let config = Config {
|
let config = Config {
|
||||||
baudrate: 115200,
|
baudrate: 115200,
|
||||||
|
@ -7,9 +7,9 @@ use esp32c3_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
system::SystemExt,
|
system::SystemExt,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
@ -23,13 +23,15 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
// Set GPIO5 as an output, and set its state high initially.
|
// Set GPIO5 as an output, and set its state high initially.
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -11,11 +11,11 @@ use esp32c3_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
@ -32,14 +32,16 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
// Set GPIO5 as an output
|
// Set GPIO5 as an output
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -16,11 +16,11 @@ use esp32c3_hal::{
|
|||||||
pac,
|
pac,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
pulse_control::ClockSource,
|
pulse_control::ClockSource,
|
||||||
|
timer::TimerGroup,
|
||||||
utils::{smartLedAdapter, SmartLedsAdapter},
|
utils::{smartLedAdapter, SmartLedsAdapter},
|
||||||
Delay,
|
Delay,
|
||||||
PulseControl,
|
PulseControl,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
IO,
|
IO,
|
||||||
};
|
};
|
||||||
#[allow(unused_imports)]
|
#[allow(unused_imports)]
|
||||||
@ -40,13 +40,14 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
|
||||||
// Disable watchdogs
|
// Disable watchdogs
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
|
|
||||||
// Configure RMT peripheral globally
|
// Configure RMT peripheral globally
|
||||||
let pulse = PulseControl::new(
|
let pulse = PulseControl::new(
|
||||||
|
@ -3,7 +3,14 @@
|
|||||||
|
|
||||||
use core::fmt::Write;
|
use core::fmt::Write;
|
||||||
|
|
||||||
use esp32c3_hal::{clock::ClockControl, pac::Peripherals, prelude::*, RtcCntl, Serial, Timer};
|
use esp32c3_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
@ -16,14 +23,17 @@ fn main() -> ! {
|
|||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
// Disable watchdog timers
|
// Disable watchdog timers
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
timer0.start(1u64.secs());
|
timer0.start(1u64.secs());
|
||||||
|
|
||||||
|
@ -25,8 +25,8 @@ use esp32c3_hal::{
|
|||||||
i2c::I2C,
|
i2c::I2C,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -40,14 +40,17 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
// Disable watchdog timers
|
// Disable watchdog timers
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
|
||||||
|
@ -8,8 +8,8 @@ use esp32c3_hal::{
|
|||||||
pac::{Peripherals, UART0},
|
pac::{Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
ram,
|
ram,
|
||||||
|
timer::TimerGroup,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -30,11 +30,14 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT flash boot protection
|
// Disable MWDT flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
// The RWDT flash boot protection remains enabled and it being triggered is part
|
// The RWDT flash boot protection remains enabled and it being triggered is part
|
||||||
// of the example
|
// of the example
|
||||||
|
|
||||||
|
@ -8,9 +8,9 @@ use esp32c3_hal::{
|
|||||||
efuse::Efuse,
|
efuse::Efuse,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
@ -23,14 +23,16 @@ fn main() -> ! {
|
|||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
// Disable watchdog timers
|
// Disable watchdog timers
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
||||||
writeln!(
|
writeln!(
|
||||||
|
@ -14,10 +14,10 @@ use esp32c3_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
serial::config::AtCmdConfig,
|
serial::config::AtCmdConfig,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -33,14 +33,17 @@ fn main() -> ! {
|
|||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
// Disable watchdog timers
|
// Disable watchdog timers
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
||||||
serial0.set_rx_fifo_full_threshold(30);
|
serial0.set_rx_fifo_full_threshold(30);
|
||||||
|
@ -24,10 +24,10 @@ use esp32c3_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
spi::{Spi, SpiMode},
|
spi::{Spi, SpiMode},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
@ -41,14 +41,17 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
let sclk = io.pins.gpio6;
|
let sclk = io.pins.gpio6;
|
||||||
|
@ -10,10 +10,10 @@ use esp32c3_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
systimer::{Alarm, SystemTimer, Target},
|
systimer::{Alarm, SystemTimer, Target},
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
@ -32,14 +32,17 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
writeln!(serial0, "SYSTIMER Demo start!").ok();
|
writeln!(serial0, "SYSTIMER Demo start!").ok();
|
||||||
|
|
||||||
|
@ -9,17 +9,18 @@ use esp32c3_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::{Timer0, TimerGroup},
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
use esp_hal_common::Timer;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use riscv_rt::entry;
|
use riscv_rt::entry;
|
||||||
|
|
||||||
static mut SERIAL: Mutex<RefCell<Option<Serial<UART0>>>> = Mutex::new(RefCell::new(None));
|
static mut SERIAL: Mutex<RefCell<Option<Serial<UART0>>>> = Mutex::new(RefCell::new(None));
|
||||||
static mut TIMER0: Mutex<RefCell<Option<Timer<TIMG0>>>> = Mutex::new(RefCell::new(None));
|
static mut TIMER0: Mutex<RefCell<Option<Timer<Timer0<TIMG0>>>>> = Mutex::new(RefCell::new(None));
|
||||||
static mut TIMER1: Mutex<RefCell<Option<Timer<TIMG1>>>> = Mutex::new(RefCell::new(None));
|
static mut TIMER1: Mutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> = Mutex::new(RefCell::new(None));
|
||||||
|
|
||||||
#[entry]
|
#[entry]
|
||||||
fn main() -> ! {
|
fn main() -> ! {
|
||||||
@ -30,14 +31,19 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut timer1 = timer_group1.timer0;
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
|
@ -7,9 +7,9 @@ use esp32c3_hal::{
|
|||||||
clock::ClockControl,
|
clock::ClockControl,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
UsbSerialJtag,
|
UsbSerialJtag,
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -23,14 +23,16 @@ fn main() -> ! {
|
|||||||
|
|
||||||
let mut delay = Delay::new(&clocks);
|
let mut delay = Delay::new(&clocks);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
// Disable watchdog timers
|
// Disable watchdog timers
|
||||||
rtc_cntl.set_super_wdt_enable(false);
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
rtc_cntl.set_wdt_enable(false);
|
rtc_cntl.set_wdt_enable(false);
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
|
|
||||||
loop {
|
loop {
|
||||||
writeln!(UsbSerialJtag, "Hello world!").ok();
|
writeln!(UsbSerialJtag, "Hello world!").ok();
|
||||||
|
49
esp32c3-hal/examples/watchdog.rs
Normal file
49
esp32c3-hal/examples/watchdog.rs
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
//! This demos the watchdog timer.
|
||||||
|
//! Basically the same as `hello_world` but if you remove the call to
|
||||||
|
//! `wdt.feed()` the watchdog will reset the system.
|
||||||
|
|
||||||
|
#![no_std]
|
||||||
|
#![no_main]
|
||||||
|
|
||||||
|
use core::fmt::Write;
|
||||||
|
|
||||||
|
use esp32c3_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
|
use nb::block;
|
||||||
|
use panic_halt as _;
|
||||||
|
use riscv_rt::entry;
|
||||||
|
|
||||||
|
#[entry]
|
||||||
|
fn main() -> ! {
|
||||||
|
let peripherals = Peripherals::take().unwrap();
|
||||||
|
let system = peripherals.SYSTEM.split();
|
||||||
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
|
// Disable watchdog timers
|
||||||
|
rtc_cntl.set_super_wdt_enable(false);
|
||||||
|
rtc_cntl.set_wdt_enable(false);
|
||||||
|
wdt0.start(2u64.secs());
|
||||||
|
wdt1.disable();
|
||||||
|
|
||||||
|
timer0.start(1u64.secs());
|
||||||
|
|
||||||
|
loop {
|
||||||
|
wdt0.feed();
|
||||||
|
writeln!(serial0, "Hello world!").unwrap();
|
||||||
|
block!(timer0.wait()).unwrap();
|
||||||
|
}
|
||||||
|
}
|
@ -17,13 +17,13 @@ pub use esp_hal_common::{
|
|||||||
spi,
|
spi,
|
||||||
system,
|
system,
|
||||||
systimer,
|
systimer,
|
||||||
|
timer,
|
||||||
utils,
|
utils,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
PulseControl,
|
PulseControl,
|
||||||
Rng,
|
Rng,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
UsbSerialJtag,
|
UsbSerialJtag,
|
||||||
};
|
};
|
||||||
#[cfg(feature = "direct-boot")]
|
#[cfg(feature = "direct-boot")]
|
||||||
|
@ -11,9 +11,9 @@ use esp32s2_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -25,11 +25,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -16,10 +16,10 @@ use esp32s2_hal::{
|
|||||||
config::{Config, DataBits, Parity, StopBits},
|
config::{Config, DataBits, Parity, StopBits},
|
||||||
TxRxPins,
|
TxRxPins,
|
||||||
},
|
},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -31,11 +31,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let config = Config {
|
let config = Config {
|
||||||
|
@ -6,9 +6,9 @@ use esp32s2_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -19,11 +19,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Set GPIO4 as an output, and set its state high initially.
|
// Set GPIO4 as an output, and set its state high initially.
|
||||||
|
@ -11,9 +11,9 @@ use esp32s2_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -24,11 +24,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -10,11 +10,11 @@ use esp32s2_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
|
use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
|
||||||
@ -31,12 +31,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Set GPIO4 as an output, and set its state high initially.
|
// Set GPIO4 as an output, and set its state high initially.
|
||||||
|
@ -15,11 +15,11 @@ use esp32s2_hal::{
|
|||||||
clock::ClockControl,
|
clock::ClockControl,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
utils::{smartLedAdapter, SmartLedsAdapter},
|
utils::{smartLedAdapter, SmartLedsAdapter},
|
||||||
Delay,
|
Delay,
|
||||||
PulseControl,
|
PulseControl,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
IO,
|
IO,
|
||||||
};
|
};
|
||||||
#[allow(unused_imports)]
|
#[allow(unused_imports)]
|
||||||
@ -39,11 +39,12 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Configure RMT peripheral globally
|
// Configure RMT peripheral globally
|
||||||
|
@ -3,7 +3,14 @@
|
|||||||
|
|
||||||
use core::fmt::Write;
|
use core::fmt::Write;
|
||||||
|
|
||||||
use esp32s2_hal::{clock::ClockControl, pac::Peripherals, prelude::*, RtcCntl, Serial, Timer};
|
use esp32s2_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -14,12 +21,14 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
timer0.start(1u64.secs());
|
timer0.start(1u64.secs());
|
||||||
|
@ -27,9 +27,9 @@ use esp32s2_hal::{
|
|||||||
i2c::I2C,
|
i2c::I2C,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -42,12 +42,14 @@ fn main() -> ! {
|
|||||||
let mut system = peripherals.SYSTEM.split();
|
let mut system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable watchdog timer
|
// Disable watchdog timer
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -8,8 +8,8 @@ use esp32s2_hal::{
|
|||||||
pac::{Peripherals, UART0},
|
pac::{Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
ram,
|
ram,
|
||||||
|
timer::TimerGroup,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -30,11 +30,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT flash boot protection
|
// Disable MWDT flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
// The RWDT flash boot protection remains enabled and it being triggered is part
|
// The RWDT flash boot protection remains enabled and it being triggered is part
|
||||||
// of the example
|
// of the example
|
||||||
|
|
||||||
|
@ -8,9 +8,9 @@ use esp32s2_hal::{
|
|||||||
efuse::Efuse,
|
efuse::Efuse,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -21,12 +21,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
||||||
writeln!(
|
writeln!(
|
||||||
|
@ -13,10 +13,10 @@ use esp32s2_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
serial::config::AtCmdConfig,
|
serial::config::AtCmdConfig,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -33,14 +33,17 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
||||||
|
@ -24,10 +24,10 @@ use esp32s2_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
spi::{Spi, SpiMode},
|
spi::{Spi, SpiMode},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -41,10 +41,11 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -9,11 +9,11 @@ use esp32s2_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
systimer::{Alarm, SystemTimer, Target},
|
systimer::{Alarm, SystemTimer, Target},
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
|
use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
|
||||||
@ -34,12 +34,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let syst = SystemTimer::new(peripherals.SYSTIMER);
|
let syst = SystemTimer::new(peripherals.SYSTIMER);
|
||||||
|
@ -8,20 +8,25 @@ use esp32s2_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::{Timer0, Timer1, TimerGroup},
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
use esp_hal_common::Timer;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
|
use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
|
|
||||||
static mut SERIAL: CriticalSectionMutex<RefCell<Option<Serial<UART0>>>> =
|
static mut SERIAL: CriticalSectionMutex<RefCell<Option<Serial<UART0>>>> =
|
||||||
CriticalSectionMutex::new(RefCell::new(None));
|
CriticalSectionMutex::new(RefCell::new(None));
|
||||||
static mut TIMER0: CriticalSectionMutex<RefCell<Option<Timer<TIMG0>>>> =
|
static mut TIMER00: CriticalSectionMutex<RefCell<Option<Timer<Timer0<TIMG0>>>>> =
|
||||||
CriticalSectionMutex::new(RefCell::new(None));
|
CriticalSectionMutex::new(RefCell::new(None));
|
||||||
static mut TIMER1: CriticalSectionMutex<RefCell<Option<Timer<TIMG1>>>> =
|
static mut TIMER01: CriticalSectionMutex<RefCell<Option<Timer<Timer1<TIMG0>>>>> =
|
||||||
|
CriticalSectionMutex::new(RefCell::new(None));
|
||||||
|
static mut TIMER10: CriticalSectionMutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> =
|
||||||
|
CriticalSectionMutex::new(RefCell::new(None));
|
||||||
|
static mut TIMER11: CriticalSectionMutex<RefCell<Option<Timer<Timer1<TIMG1>>>>> =
|
||||||
CriticalSectionMutex::new(RefCell::new(None));
|
CriticalSectionMutex::new(RefCell::new(None));
|
||||||
|
|
||||||
#[entry]
|
#[entry]
|
||||||
@ -31,14 +36,22 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer00 = timer_group0.timer0;
|
||||||
|
let mut timer01 = timer_group0.timer1;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut timer10 = timer_group1.timer0;
|
||||||
|
let mut timer11 = timer_group1.timer1;
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
@ -46,21 +59,37 @@ fn main() -> ! {
|
|||||||
pac::Interrupt::TG0_T0_LEVEL,
|
pac::Interrupt::TG0_T0_LEVEL,
|
||||||
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
);
|
);
|
||||||
timer0.start(500u64.millis());
|
interrupt::enable(
|
||||||
timer0.listen();
|
Cpu::ProCpu,
|
||||||
|
pac::Interrupt::TG0_T1_LEVEL,
|
||||||
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
|
);
|
||||||
|
timer00.start(500u64.millis());
|
||||||
|
timer00.listen();
|
||||||
|
timer01.start(2500u64.millis());
|
||||||
|
timer01.listen();
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
pac::Interrupt::TG1_T0_LEVEL,
|
pac::Interrupt::TG1_T0_LEVEL,
|
||||||
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
);
|
);
|
||||||
timer1.start(1u64.secs());
|
interrupt::enable(
|
||||||
timer1.listen();
|
Cpu::ProCpu,
|
||||||
|
pac::Interrupt::TG1_T1_LEVEL,
|
||||||
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
|
);
|
||||||
|
timer10.start(1u64.secs());
|
||||||
|
timer10.listen();
|
||||||
|
timer11.start(3u64.secs());
|
||||||
|
timer11.listen();
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&SERIAL).lock(|data| (*data).replace(Some(serial0)));
|
(&SERIAL).lock(|data| (*data).replace(Some(serial0)));
|
||||||
(&TIMER0).lock(|data| (*data).replace(Some(timer0)));
|
(&TIMER00).lock(|data| (*data).replace(Some(timer00)));
|
||||||
(&TIMER1).lock(|data| (*data).replace(Some(timer1)));
|
(&TIMER01).lock(|data| (*data).replace(Some(timer01)));
|
||||||
|
(&TIMER10).lock(|data| (*data).replace(Some(timer10)));
|
||||||
|
(&TIMER11).lock(|data| (*data).replace(Some(timer11)));
|
||||||
}
|
}
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
@ -74,50 +103,84 @@ fn main() -> ! {
|
|||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn level2_interrupt() {
|
pub fn level2_interrupt() {
|
||||||
unsafe {
|
|
||||||
(&SERIAL).lock(|data| {
|
|
||||||
let mut serial = data.borrow_mut();
|
|
||||||
let serial = serial.as_mut().unwrap();
|
|
||||||
writeln!(serial, "Interrupt Level 2").ok();
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
interrupt::clear(
|
interrupt::clear(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
);
|
);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&TIMER0).lock(|data| {
|
(&TIMER00).lock(|data| {
|
||||||
let mut timer0 = data.borrow_mut();
|
let mut timer = data.borrow_mut();
|
||||||
let timer0 = timer0.as_mut().unwrap();
|
let timer = timer.as_mut().unwrap();
|
||||||
timer0.clear_interrupt();
|
|
||||||
timer0.start(500u64.millis());
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(500u64.millis());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 2 - Timer0").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
|
});
|
||||||
|
|
||||||
|
(&TIMER01).lock(|data| {
|
||||||
|
let mut timer = data.borrow_mut();
|
||||||
|
let timer = timer.as_mut().unwrap();
|
||||||
|
|
||||||
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(2500u64.millis());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 2 - Timer1").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn level3_interrupt() {
|
pub fn level3_interrupt() {
|
||||||
unsafe {
|
|
||||||
(&SERIAL).lock(|data| {
|
|
||||||
let mut serial = data.borrow_mut();
|
|
||||||
let serial = serial.as_mut().unwrap();
|
|
||||||
writeln!(serial, "Interrupt Level 3").ok();
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
interrupt::clear(
|
interrupt::clear(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
);
|
);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&TIMER1).lock(|data| {
|
(&TIMER10).lock(|data| {
|
||||||
let mut timer1 = data.borrow_mut();
|
let mut timer = data.borrow_mut();
|
||||||
let timer1 = timer1.as_mut().unwrap();
|
let timer = timer.as_mut().unwrap();
|
||||||
timer1.clear_interrupt();
|
|
||||||
timer1.start(1u64.secs());
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(1u64.secs());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 3 - Timer0").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
|
});
|
||||||
|
|
||||||
|
(&TIMER11).lock(|data| {
|
||||||
|
let mut timer = data.borrow_mut();
|
||||||
|
let timer = timer.as_mut().unwrap();
|
||||||
|
|
||||||
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(3u64.secs());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 3 - Timer1").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
44
esp32s2-hal/examples/watchdog.rs
Normal file
44
esp32s2-hal/examples/watchdog.rs
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
//! This demos the watchdog timer.
|
||||||
|
//! Basically the same as `hello_world` but if you remove the call to
|
||||||
|
//! `wdt.feed()` the watchdog will reset the system.#![no_std]
|
||||||
|
|
||||||
|
#![no_std]
|
||||||
|
#![no_main]
|
||||||
|
|
||||||
|
use core::fmt::Write;
|
||||||
|
|
||||||
|
use esp32s2_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
|
use nb::block;
|
||||||
|
use panic_halt as _;
|
||||||
|
use xtensa_lx_rt::entry;
|
||||||
|
|
||||||
|
#[entry]
|
||||||
|
fn main() -> ! {
|
||||||
|
let peripherals = Peripherals::take().unwrap();
|
||||||
|
let system = peripherals.SYSTEM.split();
|
||||||
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
|
wdt.start(2u64.secs());
|
||||||
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
|
timer0.start(1u64.secs());
|
||||||
|
|
||||||
|
loop {
|
||||||
|
wdt.feed();
|
||||||
|
writeln!(serial0, "Hello world!").unwrap();
|
||||||
|
block!(timer0.wait()).unwrap();
|
||||||
|
}
|
||||||
|
}
|
@ -14,6 +14,7 @@ pub use esp_hal_common::{
|
|||||||
serial,
|
serial,
|
||||||
spi,
|
spi,
|
||||||
systimer,
|
systimer,
|
||||||
|
timer,
|
||||||
utils,
|
utils,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
@ -21,7 +22,6 @@ pub use esp_hal_common::{
|
|||||||
Rng,
|
Rng,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pub use self::gpio::IO;
|
pub use self::gpio::IO;
|
||||||
|
@ -16,10 +16,10 @@ use esp32s3_hal::{
|
|||||||
config::{Config, DataBits, Parity, StopBits},
|
config::{Config, DataBits, Parity, StopBits},
|
||||||
TxRxPins,
|
TxRxPins,
|
||||||
},
|
},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -31,11 +31,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let config = Config {
|
let config = Config {
|
||||||
|
@ -6,9 +6,9 @@ use esp32s3_hal::{
|
|||||||
gpio::IO,
|
gpio::IO,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -19,11 +19,12 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Set GPIO4 as an output, and set its state high initially.
|
// Set GPIO4 as an output, and set its state high initially.
|
||||||
|
@ -10,11 +10,11 @@ use esp32s3_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
||||||
@ -31,12 +31,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Set GPIO4 as an output, and set its state high initially.
|
// Set GPIO4 as an output, and set its state high initially.
|
||||||
|
@ -16,11 +16,11 @@ use esp32s3_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
pulse_control::ClockSource,
|
pulse_control::ClockSource,
|
||||||
|
timer::TimerGroup,
|
||||||
utils::{smartLedAdapter, SmartLedsAdapter},
|
utils::{smartLedAdapter, SmartLedsAdapter},
|
||||||
Delay,
|
Delay,
|
||||||
PulseControl,
|
PulseControl,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
IO,
|
IO,
|
||||||
};
|
};
|
||||||
#[allow(unused_imports)]
|
#[allow(unused_imports)]
|
||||||
@ -40,11 +40,12 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
// Configure RMT peripheral globally
|
// Configure RMT peripheral globally
|
||||||
|
@ -3,7 +3,14 @@
|
|||||||
|
|
||||||
use core::fmt::Write;
|
use core::fmt::Write;
|
||||||
|
|
||||||
use esp32s3_hal::{clock::ClockControl, pac::Peripherals, prelude::*, RtcCntl, Serial, Timer};
|
use esp32s3_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -14,12 +21,14 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
timer0.start(1u64.secs());
|
timer0.start(1u64.secs());
|
||||||
|
@ -27,9 +27,9 @@ use esp32s3_hal::{
|
|||||||
i2c::I2C,
|
i2c::I2C,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -42,12 +42,14 @@ fn main() -> ! {
|
|||||||
let mut system = peripherals.SYSTEM.split();
|
let mut system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable watchdog timer
|
// Disable watchdog timer
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -7,10 +7,11 @@ use esp32s3_hal::{
|
|||||||
clock::ClockControl,
|
clock::ClockControl,
|
||||||
pac::{Peripherals, TIMG1},
|
pac::{Peripherals, TIMG1},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::{Timer0, TimerGroup},
|
||||||
CpuControl,
|
CpuControl,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
use esp_hal_common::Timer;
|
||||||
use esp_println::println;
|
use esp_println::println;
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -23,13 +24,19 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut timer1 = timer_group1.timer0;
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
timer0.start(1u64.secs());
|
timer0.start(1u64.secs());
|
||||||
@ -51,7 +58,10 @@ fn main() -> ! {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn cpu1_task(timer: &mut Timer<TIMG1>, counter: &xtensa_lx::mutex::SpinLockMutex<AtomicI32>) -> ! {
|
fn cpu1_task(
|
||||||
|
timer: &mut Timer<Timer0<TIMG1>>,
|
||||||
|
counter: &xtensa_lx::mutex::SpinLockMutex<AtomicI32>,
|
||||||
|
) -> ! {
|
||||||
println!("Hello World - Core 1!");
|
println!("Hello World - Core 1!");
|
||||||
loop {
|
loop {
|
||||||
block!(timer.wait()).unwrap();
|
block!(timer.wait()).unwrap();
|
||||||
|
@ -8,8 +8,8 @@ use esp32s3_hal::{
|
|||||||
pac::{Peripherals, UART0},
|
pac::{Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
ram,
|
ram,
|
||||||
|
timer::TimerGroup,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -30,11 +30,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT flash boot protection
|
// Disable MWDT flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
// The RWDT flash boot protection remains enabled and it being triggered is part
|
// The RWDT flash boot protection remains enabled and it being triggered is part
|
||||||
// of the example
|
// of the example
|
||||||
|
|
||||||
|
@ -8,9 +8,9 @@ use esp32s3_hal::{
|
|||||||
efuse::Efuse,
|
efuse::Efuse,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -21,12 +21,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
writeln!(serial0, "MAC address {:02x?}", Efuse::get_mac_address()).unwrap();
|
||||||
writeln!(
|
writeln!(
|
||||||
|
@ -13,10 +13,10 @@ use esp32s3_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
serial::config::AtCmdConfig,
|
serial::config::AtCmdConfig,
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use nb::block;
|
use nb::block;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -33,14 +33,19 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
|
||||||
|
@ -24,10 +24,10 @@ use esp32s3_hal::{
|
|||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
spi::{Spi, SpiMode},
|
spi::{Spi, SpiMode},
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
@ -41,10 +41,11 @@ fn main() -> ! {
|
|||||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||||
// the RTC WDT, and the TIMG WDTs.
|
// the RTC WDT, and the TIMG WDTs.
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut serial0 = Serial::new(peripherals.UART0);
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||||
|
@ -9,11 +9,11 @@ use esp32s3_hal::{
|
|||||||
pac::{self, Peripherals, UART0},
|
pac::{self, Peripherals, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
systimer::{Alarm, SystemTimer, Target},
|
systimer::{Alarm, SystemTimer, Target},
|
||||||
|
timer::TimerGroup,
|
||||||
Cpu,
|
Cpu,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
||||||
@ -34,12 +34,13 @@ fn main() -> ! {
|
|||||||
let system = peripherals.SYSTEM.split();
|
let system = peripherals.SYSTEM.split();
|
||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
let syst = SystemTimer::new(peripherals.SYSTIMER);
|
let syst = SystemTimer::new(peripherals.SYSTIMER);
|
||||||
|
@ -8,20 +8,25 @@ use esp32s3_hal::{
|
|||||||
interrupt,
|
interrupt,
|
||||||
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
pac::{self, Peripherals, TIMG0, TIMG1, UART0},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::{Timer0, Timer1, TimerGroup},
|
||||||
Cpu,
|
Cpu,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
};
|
};
|
||||||
|
use esp_hal_common::Timer;
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
use xtensa_lx::mutex::{Mutex, SpinLockMutex};
|
||||||
use xtensa_lx_rt::entry;
|
use xtensa_lx_rt::entry;
|
||||||
|
|
||||||
static mut SERIAL: SpinLockMutex<RefCell<Option<Serial<UART0>>>> =
|
static mut SERIAL: SpinLockMutex<RefCell<Option<Serial<UART0>>>> =
|
||||||
SpinLockMutex::new(RefCell::new(None));
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
static mut TIMER0: SpinLockMutex<RefCell<Option<Timer<TIMG0>>>> =
|
static mut TIMER00: SpinLockMutex<RefCell<Option<Timer<Timer0<TIMG0>>>>> =
|
||||||
SpinLockMutex::new(RefCell::new(None));
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
static mut TIMER1: SpinLockMutex<RefCell<Option<Timer<TIMG1>>>> =
|
static mut TIMER01: SpinLockMutex<RefCell<Option<Timer<Timer1<TIMG0>>>>> =
|
||||||
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
|
static mut TIMER10: SpinLockMutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> =
|
||||||
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
|
static mut TIMER11: SpinLockMutex<RefCell<Option<Timer<Timer1<TIMG1>>>>> =
|
||||||
SpinLockMutex::new(RefCell::new(None));
|
SpinLockMutex::new(RefCell::new(None));
|
||||||
|
|
||||||
#[entry]
|
#[entry]
|
||||||
@ -31,14 +36,22 @@ fn main() -> ! {
|
|||||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
// Disable the TIMG watchdog timer.
|
// Disable the TIMG watchdog timer.
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
let mut timer1 = Timer::new(peripherals.TIMG1, clocks.apb_clock);
|
let mut timer00 = timer_group0.timer0;
|
||||||
|
let mut timer01 = timer_group0.timer1;
|
||||||
|
let mut wdt0 = timer_group0.wdt;
|
||||||
|
|
||||||
|
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||||
|
let mut timer10 = timer_group1.timer0;
|
||||||
|
let mut timer11 = timer_group1.timer1;
|
||||||
|
let mut wdt1 = timer_group1.wdt;
|
||||||
|
|
||||||
let serial0 = Serial::new(peripherals.UART0);
|
let serial0 = Serial::new(peripherals.UART0);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt0.disable();
|
||||||
timer1.disable();
|
wdt1.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
@ -46,21 +59,37 @@ fn main() -> ! {
|
|||||||
pac::Interrupt::TG0_T0_LEVEL,
|
pac::Interrupt::TG0_T0_LEVEL,
|
||||||
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
);
|
);
|
||||||
timer0.start(500u64.millis());
|
interrupt::enable(
|
||||||
timer0.listen();
|
Cpu::ProCpu,
|
||||||
|
pac::Interrupt::TG0_T1_LEVEL,
|
||||||
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
|
);
|
||||||
|
timer00.start(500u64.millis());
|
||||||
|
timer00.listen();
|
||||||
|
timer01.start(2500u64.millis());
|
||||||
|
timer01.listen();
|
||||||
|
|
||||||
interrupt::enable(
|
interrupt::enable(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
pac::Interrupt::TG1_T0_LEVEL,
|
pac::Interrupt::TG1_T0_LEVEL,
|
||||||
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
);
|
);
|
||||||
timer1.start(1u64.secs());
|
interrupt::enable(
|
||||||
timer1.listen();
|
Cpu::ProCpu,
|
||||||
|
pac::Interrupt::TG1_T1_LEVEL,
|
||||||
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
|
);
|
||||||
|
timer10.start(1u64.secs());
|
||||||
|
timer10.listen();
|
||||||
|
timer11.start(3u64.secs());
|
||||||
|
timer11.listen();
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&SERIAL).lock(|data| (*data).replace(Some(serial0)));
|
(&SERIAL).lock(|data| (*data).replace(Some(serial0)));
|
||||||
(&TIMER0).lock(|data| (*data).replace(Some(timer0)));
|
(&TIMER00).lock(|data| (*data).replace(Some(timer00)));
|
||||||
(&TIMER1).lock(|data| (*data).replace(Some(timer1)));
|
(&TIMER01).lock(|data| (*data).replace(Some(timer01)));
|
||||||
|
(&TIMER10).lock(|data| (*data).replace(Some(timer10)));
|
||||||
|
(&TIMER11).lock(|data| (*data).replace(Some(timer11)));
|
||||||
}
|
}
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
@ -74,50 +103,84 @@ fn main() -> ! {
|
|||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn level2_interrupt() {
|
pub fn level2_interrupt() {
|
||||||
unsafe {
|
|
||||||
(&SERIAL).lock(|data| {
|
|
||||||
let mut serial = data.borrow_mut();
|
|
||||||
let serial = serial.as_mut().unwrap();
|
|
||||||
writeln!(serial, "Interrupt Level 2").ok();
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
interrupt::clear(
|
interrupt::clear(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
interrupt::CpuInterrupt::Interrupt20LevelPriority2,
|
||||||
);
|
);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&TIMER0).lock(|data| {
|
(&TIMER00).lock(|data| {
|
||||||
let mut timer0 = data.borrow_mut();
|
let mut timer = data.borrow_mut();
|
||||||
let timer0 = timer0.as_mut().unwrap();
|
let timer = timer.as_mut().unwrap();
|
||||||
timer0.clear_interrupt();
|
|
||||||
timer0.start(500u64.millis());
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(500u64.millis());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 2 - Timer0").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
|
});
|
||||||
|
|
||||||
|
(&TIMER01).lock(|data| {
|
||||||
|
let mut timer = data.borrow_mut();
|
||||||
|
let timer = timer.as_mut().unwrap();
|
||||||
|
|
||||||
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(2500u64.millis());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 2 - Timer1").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn level3_interrupt() {
|
pub fn level3_interrupt() {
|
||||||
unsafe {
|
|
||||||
(&SERIAL).lock(|data| {
|
|
||||||
let mut serial = data.borrow_mut();
|
|
||||||
let serial = serial.as_mut().unwrap();
|
|
||||||
writeln!(serial, "Interrupt Level 3").ok();
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
interrupt::clear(
|
interrupt::clear(
|
||||||
Cpu::ProCpu,
|
Cpu::ProCpu,
|
||||||
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
|
||||||
);
|
);
|
||||||
|
|
||||||
unsafe {
|
unsafe {
|
||||||
(&TIMER1).lock(|data| {
|
(&TIMER10).lock(|data| {
|
||||||
let mut timer1 = data.borrow_mut();
|
let mut timer = data.borrow_mut();
|
||||||
let timer1 = timer1.as_mut().unwrap();
|
let timer = timer.as_mut().unwrap();
|
||||||
timer1.clear_interrupt();
|
|
||||||
timer1.start(1u64.secs());
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(1u64.secs());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 3 - Timer0").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
|
});
|
||||||
|
|
||||||
|
(&TIMER11).lock(|data| {
|
||||||
|
let mut timer = data.borrow_mut();
|
||||||
|
let timer = timer.as_mut().unwrap();
|
||||||
|
|
||||||
|
if timer.is_interrupt_set() {
|
||||||
|
timer.clear_interrupt();
|
||||||
|
timer.start(3u64.secs());
|
||||||
|
|
||||||
|
(&SERIAL).lock(|data| {
|
||||||
|
let mut serial = data.borrow_mut();
|
||||||
|
let serial = serial.as_mut().unwrap();
|
||||||
|
writeln!(serial, "Interrupt Level 3 - Timer1").ok();
|
||||||
|
});
|
||||||
|
}
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -7,9 +7,9 @@ use esp32s3_hal::{
|
|||||||
clock::ClockControl,
|
clock::ClockControl,
|
||||||
pac::Peripherals,
|
pac::Peripherals,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
Delay,
|
Delay,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Timer,
|
|
||||||
UsbSerialJtag,
|
UsbSerialJtag,
|
||||||
};
|
};
|
||||||
use panic_halt as _;
|
use panic_halt as _;
|
||||||
@ -23,10 +23,11 @@ fn main() -> ! {
|
|||||||
|
|
||||||
let mut delay = Delay::new(&clocks);
|
let mut delay = Delay::new(&clocks);
|
||||||
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
let mut timer0 = Timer::new(peripherals.TIMG0, clocks.apb_clock);
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
|
|
||||||
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
// Disable MWDT and RWDT (Watchdog) flash boot protection
|
||||||
timer0.disable();
|
wdt.disable();
|
||||||
rtc_cntl.set_wdt_global_enable(false);
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
loop {
|
loop {
|
||||||
|
44
esp32s3-hal/examples/watchdog.rs
Normal file
44
esp32s3-hal/examples/watchdog.rs
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
//! This demos the watchdog timer.
|
||||||
|
//! Basically the same as `hello_world` but if you remove the call to
|
||||||
|
//! `wdt.feed()` the watchdog will reset the system.#![no_std]
|
||||||
|
|
||||||
|
#![no_std]
|
||||||
|
#![no_main]
|
||||||
|
|
||||||
|
use core::fmt::Write;
|
||||||
|
|
||||||
|
use esp32s3_hal::{
|
||||||
|
clock::ClockControl,
|
||||||
|
pac::Peripherals,
|
||||||
|
prelude::*,
|
||||||
|
timer::TimerGroup,
|
||||||
|
RtcCntl,
|
||||||
|
Serial,
|
||||||
|
};
|
||||||
|
use nb::block;
|
||||||
|
use panic_halt as _;
|
||||||
|
use xtensa_lx_rt::entry;
|
||||||
|
|
||||||
|
#[entry]
|
||||||
|
fn main() -> ! {
|
||||||
|
let peripherals = Peripherals::take().unwrap();
|
||||||
|
let system = peripherals.SYSTEM.split();
|
||||||
|
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||||
|
|
||||||
|
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||||
|
let mut timer0 = timer_group0.timer0;
|
||||||
|
let mut wdt = timer_group0.wdt;
|
||||||
|
let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
|
||||||
|
let mut serial0 = Serial::new(peripherals.UART0);
|
||||||
|
|
||||||
|
wdt.start(2u64.secs());
|
||||||
|
rtc_cntl.set_wdt_global_enable(false);
|
||||||
|
|
||||||
|
timer0.start(1u64.secs());
|
||||||
|
|
||||||
|
loop {
|
||||||
|
wdt.feed();
|
||||||
|
writeln!(serial0, "Hello world!").unwrap();
|
||||||
|
block!(timer0.wait()).unwrap();
|
||||||
|
}
|
||||||
|
}
|
@ -15,6 +15,7 @@ pub use esp_hal_common::{
|
|||||||
serial,
|
serial,
|
||||||
spi,
|
spi,
|
||||||
systimer,
|
systimer,
|
||||||
|
timer,
|
||||||
usb_serial_jtag,
|
usb_serial_jtag,
|
||||||
utils,
|
utils,
|
||||||
Cpu,
|
Cpu,
|
||||||
@ -23,7 +24,6 @@ pub use esp_hal_common::{
|
|||||||
Rng,
|
Rng,
|
||||||
RtcCntl,
|
RtcCntl,
|
||||||
Serial,
|
Serial,
|
||||||
Timer,
|
|
||||||
UsbSerialJtag,
|
UsbSerialJtag,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
Loading…
x
Reference in New Issue
Block a user