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Fix Xtensa interrupts

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This commit is contained in:
bjoernQ 2022-02-18 17:48:16 +01:00 committed by Jesse Braham
parent d5938de6c0
commit 181892d02a
2 changed files with 12 additions and 10 deletions
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14
esp-hal-common/src/interrupt/xtensa.rs
View File

@ -174,42 +174,42 @@ unsafe fn core1_interrupt_peripheral() -> *const crate::pac::interrupt_core1::Re
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level1_interrupt() { fn __level_1_interrupt() {
unsafe { level1_interrupt() }; unsafe { level1_interrupt() };
} }
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level2_interrupt() { fn __level_2_interrupt() {
unsafe { level2_interrupt() }; unsafe { level2_interrupt() };
} }
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level3_interrupt() { fn __level_3_interrupt() {
unsafe { level3_interrupt() }; unsafe { level3_interrupt() };
} }
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level4_interrupt() { fn __level_4_interrupt() {
unsafe { level4_interrupt() }; unsafe { level4_interrupt() };
} }
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level5_interrupt() { fn __level_5_interrupt() {
unsafe { level5_interrupt() }; unsafe { level5_interrupt() };
} }
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level6_interrupt() { fn __level_6_interrupt() {
unsafe { level6_interrupt() }; unsafe { level6_interrupt() };
} }
#[no_mangle] #[no_mangle]
#[link_section = ".rwtext"] #[link_section = ".rwtext"]
fn __level7_interrupt() { fn __level_7_interrupt() {
unsafe { level7_interrupt() }; unsafe { level7_interrupt() };
} }

8
esp32s2-hal/examples/gpio_interrupt.rs
View File

@ -19,7 +19,7 @@ use esp_hal_common::{
PullDown, PullDown,
}; };
use panic_halt as _; use panic_halt as _;
use xtensa_lx::mutex::{Mutex, CriticalSectionMutex}; use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
use xtensa_lx_rt::entry; use xtensa_lx_rt::entry;
static mut SERIAL: CriticalSectionMutex<RefCell<Option<Serial<UART0>>>> = static mut SERIAL: CriticalSectionMutex<RefCell<Option<Serial<UART0>>>> =
@ -33,7 +33,7 @@ fn main() -> ! {
// Disable the TIMG watchdog timer. // Disable the TIMG watchdog timer.
let mut timer0 = Timer::new(peripherals.TIMG0); let mut timer0 = Timer::new(peripherals.TIMG0);
let mut serial0 = Serial::new(peripherals.UART0).unwrap(); let serial0 = Serial::new(peripherals.UART0).unwrap();
timer0.disable(); timer0.disable();
@ -61,7 +61,9 @@ fn main() -> ! {
let mut delay = Delay::new(); let mut delay = Delay::new();
unsafe { unsafe {
xtensa_lx::interrupt::enable_mask(xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask()); xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask(),
);
} }
loop { loop {