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embedded-hal SpiDevice on all esp32 variants (#106)

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* WIP: common/spi: Implement `SpiDevice`

to get shared access to an SPI bus directly via the HAL.

* WIP: common/spi: add SpiBusDevice::new

to create instances via a function call.

* esp32/examples: Add example for spi device trait

* common/spi: Finish "SpiDevice" implementation

for esp32. Abandons the approach of having the user pass in some generic
mutex in favor of creating the Mutex as part of the API so it isn't
exposed to the user in the first place.

* common/spi: Add more thorough docs

* esp32/examples: Fix example for eh1 "SpiDevice"

* common/spi: Implement `SpiDevice` for xtensa arch

and move the code into a submodule that is fenced with conditional
compilation directives.

* esp32/examples: Update spi device example

to the changed APIs for the timers and clocks, and add more transmission
tests to the example code.

* common/spi: Create devices from buscontroller

directly, instead of offering only the `new` method.

* common/spi: Finish `SpiBusDevice` trait

from embedded-hal 1.0.0-alpha.8.

* esp32: Update `SpiBusDevice` usage example.

* common/spi: Fix mutex types for xtensa32 esp

because the esp32/esp32s3 can use `SpinLockMutex`, whereas the esp32s2
has access only to `CriticalSectionMutex`.

* common/spi: Implement `SpiBusDevice` for riscv

based esp32c3.

* general: Add examples for spi device loopback

to all esp variants.

* common: Use esp_backtrace in spi_eh1_device examples

* common/spi: Update module documentation.

* common/spi: Use `critical_section::Mutex`

to unify locking across all esp variants.

* esp32c3-hal: Fix spi device example

* esp32c3/examples: Fix typo in used spi pins

Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>

Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
This commit is contained in:
har7an 2022-08-30 13:55:53 +00:00 committed by GitHub
parent 46a8470ff5
commit 8b9fd8b7a0
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 762 additions and 2 deletions
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131
esp-hal-common/src/spi.rs
View File

@ -1,7 +1,9 @@
//! # Serial Peripheral Interface
//! To construct the SPI instances, use the `Spi::new` functions.
//!
//! ## Initialisation example
//! There are multiple ways to use SPI, depending on your needs. Regardless of
//! which way you choose, you must first create an SPI instance with
//! [`Spi::new`].
//!
//! ```rust
//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
//! let sclk = io.pins.gpio12;
@ -21,6 +23,30 @@
//! &mut clocks,
//! );
//! ```
//!
//! ## Exclusive access to the SPI bus
//!
//! If all you want to do is to communicate to a single device, and you initiate
//! transactions yourself, there are a number of ways to achieve this:
//!
//! - Use the [`FullDuplex`](embedded_hal::spi::FullDuplex) trait to read/write
//! single bytes at a time,
//! - Use the [`SpiBus`](embedded_hal_1::spi::blocking::SpiBus) trait (requires
//! the "eh1" feature) and its associated functions to initiate transactions
//! with simultaneous reads and writes, or
//! - Use the [`SpiBusWrite`](embedded_hal_1::spi::blocking::SpiBusWrite) and
//! [`SpiBusRead`](embedded_hal_1::spi::blocking::SpiBusRead) traits (requires
//! the "eh1" feature) and their associated functions to read or write mutiple
//! bytes at a time.
//!
//!
//! ## Shared SPI access
//!
//! If you have multiple devices on the same SPI bus that each have their own CS
//! line, you may want to have a look at the [`SpiBusController`] and
//! [`SpiBusDevice`] implemented here. These give exclusive access to the
//! underlying SPI bus by means of a Mutex. This ensures that device
//! transactions do not interfere with each other.
use core::convert::Infallible;
@ -339,6 +365,107 @@ mod ehal1 {
self.spi.flush()
}
}
use core::cell::RefCell;
use embedded_hal_1::spi::{self, blocking::SpiDevice, ErrorType};
use crate::OutputPin;
/// SPI bus controller.
///
/// Has exclusive access to an SPI bus, which is managed via a `Mutex`. Used
/// as basis for the [`SpiBusDevice`] implementation. Note that the
/// wrapped [`RefCell`] is used solely to achieve interior mutability.
pub struct SpiBusController<B: SpiBus + ErrorType> {
lock: critical_section::Mutex<RefCell<B>>,
}
impl<B: SpiBus + ErrorType> SpiBusController<B> {
/// Create a new controller from an SPI bus instance.
///
/// Takes ownership of the SPI bus in the process. Afterwards, the SPI
/// bus can only be accessed via instances of [`SpiBusDevice`].
pub fn from_spi(bus: B) -> Self {
SpiBusController {
lock: critical_section::Mutex::new(RefCell::new(bus)),
}
}
pub fn add_device<'a, CS: OutputPin>(&'a self, cs: CS) -> SpiBusDevice<'a, B, CS> {
SpiBusDevice { bus: self, cs }
}
}
impl<B> ErrorType for SpiBusController<B>
where
B: SpiBus + ErrorType,
{
type Error = spi::ErrorKind;
}
/// An SPI device on a shared SPI bus.
///
/// Provides device specific access on a shared SPI bus. Enables attaching
/// multiple SPI devices to the same bus, each with its own CS line, and
/// performing safe transfers on them.
pub struct SpiBusDevice<'a, B, CS>
where
B: SpiBus + ErrorType,
CS: OutputPin,
{
bus: &'a SpiBusController<B>,
cs: CS,
}
impl<'a, B, CS> SpiBusDevice<'a, B, CS>
where
B: SpiBus + ErrorType,
CS: OutputPin,
{
pub fn new(bus: &'a SpiBusController<B>, cs: CS) -> Self {
SpiBusDevice { bus, cs }
}
}
impl<'a, B, CS> ErrorType for SpiBusDevice<'a, B, CS>
where
B: SpiBus + ErrorType,
CS: OutputPin,
{
type Error = spi::ErrorKind;
}
impl<B, CS> SpiDevice for SpiBusDevice<'_, B, CS>
where
B: SpiBus + ErrorType,
CS: OutputPin + crate::gpio::OutputPin,
{
type Bus = B;
fn transaction<R>(
&mut self,
f: impl FnOnce(&mut Self::Bus) -> Result<R, <Self::Bus as ErrorType>::Error>,
) -> Result<R, Self::Error> {
critical_section::with(|cs| {
let mut bus = self.bus.lock.borrow_ref_mut(cs);
self.cs.set_to_push_pull_output().set_output_high(false);
// We postpone handling these errors until AFTER we raised CS again, so the bus
// is free (Or we die trying if CS errors).
let f_res = f(&mut bus);
let flush_res = bus.flush();
self.cs.set_output_high(true);
let f_res = f_res.map_err(|_| spi::ErrorKind::Other)?;
flush_res.map_err(|_| spi::ErrorKind::Other)?;
Ok(f_res)
})
}
}
}
pub trait Instance {

4
esp32-hal/Cargo.toml
View File

@ -58,3 +58,7 @@ required-features = ["smartled"]
[[example]]
name = "spi_eh1_loopback"
required-features = ["eh1"]
[[example]]
name = "spi_eh1_device_loopback"
required-features = ["eh1"]

153
esp32-hal/examples/spi_eh1_device_loopback.rs Normal file
View File

@ -0,0 +1,153 @@
//! SPI loopback test
//!
//! Folowing pins are used:
//! SCLK GPIO19
//! MISO GPIO25
//! MOSI GPIO23
//! CS 1 GPIO12
//! CS 2 GPIO13
//! CS 3 GPIO14
//!
//! Depending on your target and the board you are using you have to change the
//! pins.
//!
//! This example transfers data via SPI.
//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
//! data.
#![no_std]
#![no_main]
use core::fmt::Write;
use esp32_hal::{
clock::ClockControl,
gpio::IO,
pac::Peripherals,
prelude::*,
spi::{Spi, SpiBusController, SpiMode},
timer::TimerGroup,
Delay,
Rtc,
Serial,
};
use esp_backtrace as _;
use xtensa_lx_rt::entry;
use embedded_hal_1::spi::blocking::SpiDevice;
#[entry]
fn main() -> ! {
let peripherals = Peripherals::take().unwrap();
let mut system = peripherals.DPORT.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
let mut wdt = timer_group0.wdt;
let mut serial0 = Serial::new(peripherals.UART0);
wdt.disable();
rtc.rwdt.disable();
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio19;
let miso = io.pins.gpio25;
let mosi = io.pins.gpio23;
let spi_controller = SpiBusController::from_spi(Spi::new_no_cs(
peripherals.SPI2,
sclk,
mosi,
miso,
1000u32.kHz(),
SpiMode::Mode0,
&mut system.peripheral_clock_control,
&clocks,
));
let mut spi_device_1 = spi_controller.add_device(io.pins.gpio12);
let mut spi_device_2 = spi_controller.add_device(io.pins.gpio13);
let mut spi_device_3 = spi_controller.add_device(io.pins.gpio14);
let mut delay = Delay::new(&clocks);
writeln!(serial0, "=== SPI example with embedded-hal-1 traits ===").unwrap();
loop {
// --- Symmetric transfer (Read as much as we write) ---
write!(serial0, "Starting symmetric transfer...").unwrap();
let write = [0xde, 0xad, 0xbe, 0xef];
let mut read: [u8; 4] = [0x00u8; 4];
spi_device_1.transfer(&mut read[..], &write[..]).unwrap();
assert_eq!(write, read);
spi_device_2.transfer(&mut read[..], &write[..]).unwrap();
spi_device_3.transfer(&mut read[..], &write[..]).unwrap();
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Asymmetric transfer (Read more than we write) ---
write!(serial0, "Starting asymetric transfer (read > write)...").unwrap();
let mut read: [u8; 4] = [0x00; 4];
spi_device_1
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
assert_eq!(write[0], read[0]);
assert_eq!(read[2], 0x00u8);
spi_device_2
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
spi_device_3
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer ---
// Only your RAM is the limit!
write!(serial0, "Starting huge transfer...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
let mut read = [0x00u8; 4096];
spi_device_1
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
assert_eq!(write, read);
spi_device_2
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer in-place (No additional allocation
// needed) ---
write!(serial0, "Starting huge transfer (in-place)...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
spi_device_1
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
for byte in 0..write.len() {
assert_eq!(write[byte], byte as u8);
}
spi_device_2
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
}
}

4
esp32c3-hal/Cargo.toml
View File

@ -59,3 +59,7 @@ required-features = ["smartled"]
[[example]]
name = "spi_eh1_loopback"
required-features = ["eh1"]
[[example]]
name = "spi_eh1_device_loopback"
required-features = ["eh1"]

158
esp32c3-hal/examples/spi_eh1_device_loopback.rs Normal file
View File

@ -0,0 +1,158 @@
//! SPI loopback test
//!
//! Folowing pins are used:
//! SCLK GPIO6
//! MISO GPIO2
//! MOSI GPIO7
//! CS 1 GPIO3
//! CS 2 GPIO4
//! CS 3 GPIO5
//!
//! Depending on your target and the board you are using you have to change the
//! pins.
//!
//! This example transfers data via SPI.
//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
//! data.
#![no_std]
#![no_main]
use core::fmt::Write;
use esp32c3_hal::{
clock::ClockControl,
gpio::IO,
pac::Peripherals,
prelude::*,
spi::{Spi, SpiBusController, SpiMode},
timer::TimerGroup,
Delay,
Rtc,
Serial,
};
use esp_backtrace as _;
use riscv_rt::entry;
use embedded_hal_1::spi::blocking::SpiDevice;
#[entry]
fn main() -> ! {
let peripherals = Peripherals::take().unwrap();
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
let mut wdt0 = timer_group0.wdt;
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
let mut wdt1 = timer_group1.wdt;
let mut serial0 = Serial::new(peripherals.UART0);
rtc.swd.disable();
rtc.rwdt.disable();
wdt0.disable();
wdt1.disable();
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio6;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio7;
let spi_controller = SpiBusController::from_spi(Spi::new_no_cs(
peripherals.SPI2,
sclk,
mosi,
miso,
1000u32.kHz(),
SpiMode::Mode0,
&mut system.peripheral_clock_control,
&clocks,
));
let mut spi_device_1 = spi_controller.add_device(io.pins.gpio3);
let mut spi_device_2 = spi_controller.add_device(io.pins.gpio4);
let mut spi_device_3 = spi_controller.add_device(io.pins.gpio5);
let mut delay = Delay::new(&clocks);
writeln!(serial0, "=== SPI example with embedded-hal-1 traits ===").unwrap();
loop {
// --- Symmetric transfer (Read as much as we write) ---
write!(serial0, "Starting symmetric transfer...").unwrap();
let write = [0xde, 0xad, 0xbe, 0xef];
let mut read: [u8; 4] = [0x00u8; 4];
spi_device_1.transfer(&mut read[..], &write[..]).unwrap();
assert_eq!(write, read);
spi_device_2.transfer(&mut read[..], &write[..]).unwrap();
spi_device_3.transfer(&mut read[..], &write[..]).unwrap();
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Asymmetric transfer (Read more than we write) ---
write!(serial0, "Starting asymetric transfer (read > write)...").unwrap();
let mut read: [u8; 4] = [0x00; 4];
spi_device_1
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
assert_eq!(write[0], read[0]);
assert_eq!(read[2], 0x00u8);
spi_device_2
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
spi_device_3
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer ---
// Only your RAM is the limit!
write!(serial0, "Starting huge transfer...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
let mut read = [0x00u8; 4096];
spi_device_1
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
assert_eq!(write, read);
spi_device_2
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer in-place (No additional allocation
// needed) ---
write!(serial0, "Starting huge transfer (in-place)...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
spi_device_1
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
for byte in 0..write.len() {
assert_eq!(write[byte], byte as u8);
}
spi_device_2
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
}
}

4
esp32s2-hal/Cargo.toml
View File

@ -57,3 +57,7 @@ required-features = ["smartled"]
[[example]]
name = "spi_eh1_loopback"
required-features = ["eh1"]
[[example]]
name = "spi_eh1_device_loopback"
required-features = ["eh1"]

153
esp32s2-hal/examples/spi_eh1_device_loopback.rs Normal file
View File

@ -0,0 +1,153 @@
//! SPI loopback test
//!
//! Folowing pins are used:
//! SCLK GPIO36
//! MISO GPIO37
//! MOSI GPIO35
//! CS 1 GPIO1
//! CS 2 GPIO2
//! CS 3 GPIO3
//!
//! Depending on your target and the board you are using you have to change the
//! pins.
//!
//! This example transfers data via SPI.
//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
//! data.
#![no_std]
#![no_main]
use core::fmt::Write;
use esp32s2_hal::{
clock::ClockControl,
gpio::IO,
pac::Peripherals,
prelude::*,
spi::{Spi, SpiBusController, SpiMode},
timer::TimerGroup,
Delay,
Rtc,
Serial,
};
use esp_backtrace as _;
use xtensa_lx_rt::entry;
use embedded_hal_1::spi::blocking::SpiDevice;
#[entry]
fn main() -> ! {
let peripherals = Peripherals::take().unwrap();
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
let mut wdt = timer_group0.wdt;
let mut serial0 = Serial::new(peripherals.UART0);
wdt.disable();
rtc.rwdt.disable();
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio36;
let miso = io.pins.gpio37;
let mosi = io.pins.gpio35;
let spi_controller = SpiBusController::from_spi(Spi::new_no_cs(
peripherals.SPI2,
sclk,
mosi,
miso,
1000u32.kHz(),
SpiMode::Mode0,
&mut system.peripheral_clock_control,
&clocks,
));
let mut spi_device_1 = spi_controller.add_device(io.pins.gpio1);
let mut spi_device_2 = spi_controller.add_device(io.pins.gpio2);
let mut spi_device_3 = spi_controller.add_device(io.pins.gpio3);
let mut delay = Delay::new(&clocks);
writeln!(serial0, "=== SPI example with embedded-hal-1 traits ===").unwrap();
loop {
// --- Symmetric transfer (Read as much as we write) ---
write!(serial0, "Starting symmetric transfer...").unwrap();
let write = [0xde, 0xad, 0xbe, 0xef];
let mut read: [u8; 4] = [0x00u8; 4];
spi_device_1.transfer(&mut read[..], &write[..]).unwrap();
assert_eq!(write, read);
spi_device_2.transfer(&mut read[..], &write[..]).unwrap();
spi_device_3.transfer(&mut read[..], &write[..]).unwrap();
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Asymmetric transfer (Read more than we write) ---
write!(serial0, "Starting asymetric transfer (read > write)...").unwrap();
let mut read: [u8; 4] = [0x00; 4];
spi_device_1
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
assert_eq!(write[0], read[0]);
assert_eq!(read[2], 0x00u8);
spi_device_2
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
spi_device_3
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer ---
// Only your RAM is the limit!
write!(serial0, "Starting huge transfer...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
let mut read = [0x00u8; 4096];
spi_device_1
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
assert_eq!(write, read);
spi_device_2
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer in-place (No additional allocation
// needed) ---
write!(serial0, "Starting huge transfer (in-place)...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
spi_device_1
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
for byte in 0..write.len() {
assert_eq!(write[byte], byte as u8);
}
spi_device_2
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
}
}

4
esp32s3-hal/Cargo.toml
View File

@ -60,3 +60,7 @@ required-features = ["smartled"]
[[example]]
name = "spi_eh1_loopback"
required-features = ["eh1"]
[[example]]
name = "spi_eh1_device_loopback"
required-features = ["eh1"]

153
esp32s3-hal/examples/spi_eh1_device_loopback.rs Normal file
View File

@ -0,0 +1,153 @@
//! SPI loopback test
//!
//! Folowing pins are used:
//! SCLK GPIO12
//! MISO GPIO11
//! MOSI GPIO13
//! CS 1 GPIO4
//! CS 2 GPIO5
//! CS 3 GPIO6
//!
//! Depending on your target and the board you are using you have to change the
//! pins.
//!
//! This example transfers data via SPI.
//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
//! data.
#![no_std]
#![no_main]
use core::fmt::Write;
use esp32s3_hal::{
clock::ClockControl,
gpio::IO,
pac::Peripherals,
prelude::*,
spi::{Spi, SpiBusController, SpiMode},
timer::TimerGroup,
Delay,
Rtc,
Serial,
};
use esp_backtrace as _;
use xtensa_lx_rt::entry;
use embedded_hal_1::spi::blocking::SpiDevice;
#[entry]
fn main() -> ! {
let peripherals = Peripherals::take().unwrap();
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
let mut wdt = timer_group0.wdt;
let mut serial0 = Serial::new(peripherals.UART0);
wdt.disable();
rtc.rwdt.disable();
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio12;
let miso = io.pins.gpio11;
let mosi = io.pins.gpio13;
let spi_controller = SpiBusController::from_spi(Spi::new_no_cs(
peripherals.SPI2,
sclk,
mosi,
miso,
1000u32.kHz(),
SpiMode::Mode0,
&mut system.peripheral_clock_control,
&clocks,
));
let mut spi_device_1 = spi_controller.add_device(io.pins.gpio4);
let mut spi_device_2 = spi_controller.add_device(io.pins.gpio5);
let mut spi_device_3 = spi_controller.add_device(io.pins.gpio6);
let mut delay = Delay::new(&clocks);
writeln!(serial0, "=== SPI example with embedded-hal-1 traits ===").unwrap();
loop {
// --- Symmetric transfer (Read as much as we write) ---
write!(serial0, "Starting symmetric transfer...").unwrap();
let write = [0xde, 0xad, 0xbe, 0xef];
let mut read: [u8; 4] = [0x00u8; 4];
spi_device_1.transfer(&mut read[..], &write[..]).unwrap();
assert_eq!(write, read);
spi_device_2.transfer(&mut read[..], &write[..]).unwrap();
spi_device_3.transfer(&mut read[..], &write[..]).unwrap();
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Asymmetric transfer (Read more than we write) ---
write!(serial0, "Starting asymetric transfer (read > write)...").unwrap();
let mut read: [u8; 4] = [0x00; 4];
spi_device_1
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
assert_eq!(write[0], read[0]);
assert_eq!(read[2], 0x00u8);
spi_device_2
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
spi_device_3
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer ---
// Only your RAM is the limit!
write!(serial0, "Starting huge transfer...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
let mut read = [0x00u8; 4096];
spi_device_1
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
assert_eq!(write, read);
spi_device_2
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
// --- Symmetric transfer with huge buffer in-place (No additional allocation
// needed) ---
write!(serial0, "Starting huge transfer (in-place)...").unwrap();
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
spi_device_1
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
for byte in 0..write.len() {
assert_eq!(write[byte], byte as u8);
}
spi_device_2
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
spi_device_3
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
writeln!(serial0, " SUCCESS").unwrap();
delay.delay_ms(250u32);
}
}