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Merge pull request #454 from MabezDev/esp32-dram-linker-fix

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ESP32 DRAM linker fix
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Björn Quentin 2023-03-24 16:59:42 +01:00 committed by GitHub
commit 91ded64b16
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6 changed files with 13 additions and 13 deletions
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2
esp32-hal/ld/link-esp32.x
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@ -28,7 +28,7 @@ INCLUDE "rtc_slow.x"
INCLUDE "external.x"
/* End of Shared sections */
_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg)-LENGTH(reserved_for_boot_seg) - 2*STACK_SIZE;
_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg) - 2*STACK_SIZE;
_stack_start_cpu1 = _heap_end;
_stack_end_cpu1 = _stack_start_cpu1 + STACK_SIZE;

11
esp32-hal/ld/memory.x
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@ -19,7 +19,16 @@ MEMORY
reserved_for_rom_seg : ORIGIN = 0x3FFAE000, len = 8k /* SRAM2; reserved for usage by the ROM */
dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM, len = 176k - RESERVE_DRAM /* SRAM2+1; first 64kB used by BT if enable */
reserved_for_boot_seg : ORIGIN = 0x3FFDC200, len = 144k /* SRAM1; reserved for static ROM usage; can be used for heap */
/*
* The following values come from the heap allocator in esp-idf: https://github.com/espressif/esp-idf/blob/ab63aaa4a24a05904da2862d627f3987ecbeafd0/components/heap/port/esp32/memory_layout.c#L137-L157
* The segment dram2_seg after the rom data space is not mentioned in the esp32 linker scripts in esp-idf, instead the space after is used as heap space.
* It seems not all rom data space is reserved, but only "core"/"important" ROM functions that may be called after booting from ROM.
*/
reserved_rom_data_pro : ORIGIN = 0X3FFE0000, len = 1088
reserved_rom_data_app : ORIGIN = 0X3FFE3F20, len = 1072
dram2_seg : ORIGIN = 0x3FFE4350, len = 111k /* the rest of DRAM after the rom data segments in the middle */
/* external flash
The 0x20 offset is a convenience for the app binary image generation.

2
esp32s2-hal/ld/link-esp32s2.x
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@ -36,7 +36,7 @@ INCLUDE "rtc_slow.x"
INCLUDE "external.x"
/* End of Shared sections */
_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg)-LENGTH(reserved_for_boot_seg) - STACK_SIZE;
_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg) - STACK_SIZE;
_stack_start_cpu0 = _heap_end;
_stack_end_cpu0 = _stack_start_cpu0 + STACK_SIZE;

7
esp32s2-hal/ld/memory.x
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@ -28,13 +28,6 @@ MEMORY
dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_CACHES + VECTORS_SIZE, len = 192k - RESERVE_CACHES - VECTORS_SIZE
/* SRAM1; reserved for static ROM usage; can be used for heap.
Length based on the "_dram0_rtos_reserved_start" symbol from IDF used to delimit the
ROM data reserved region:
https://github.com/espressif/esp-idf/blob/bcb34ca7aef4e8d3b97d75ad069b960fb1c17c16/components/heap/port/esp32s2/memory_layout.c#L121-L122
*/
reserved_for_boot_seg : ORIGIN = 0x3FFE0000, len = 0x1FA10
/* external flash
The 0x20 offset is a convenience for the app binary image generation.
Flash cache has 64KB pages. The .bin file which is flashed to the chip

2
esp32s3-hal/ld/link-esp32s3.x
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@ -51,7 +51,7 @@ INCLUDE "rtc_slow.x"
INCLUDE "external.x"
/* End of Shared sections */
_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg)-LENGTH(reserved_for_boot_seg) - 2*STACK_SIZE;
_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg) - 2*STACK_SIZE;
_stack_start_cpu1 = _heap_end;
_stack_end_cpu1 = _stack_start_cpu1 + STACK_SIZE;

2
esp32s3-hal/ld/memory.x
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@ -31,8 +31,6 @@ MEMORY
iram_seg ( RX ) : ORIGIN = 0x40370000 + RESERVE_ICACHE + VECTORS_SIZE, len = 328k - VECTORS_SIZE - RESERVE_ICACHE
dram_seg ( RW ) : ORIGIN = 0x3FC88000 , len = 345856
reserved_for_boot_seg : ORIGIN = 0x3FCDC700, len = 0xB000 /* reserved for static ROM usage; can be used for heap */
/* external flash
The 0x20 offset is a convenience for the app binary image generation.
Flash cache has 64KB pages. The .bin file which is flashed to the chip